📄 isa_lpt.tan.rpt
字号:
; N/A ; None ; 1.329 ns ; ISA_D[5] ; DATA_reg[5] ; ISA_A[15] ;
; N/A ; None ; 1.324 ns ; ISA_D[6] ; DATA_reg[6] ; ISA_A[5] ;
; N/A ; None ; 1.323 ns ; ISA_D[3] ; DATA_reg[3] ; ISA_A[5] ;
; N/A ; None ; 1.300 ns ; ISA_D[2] ; DATA_reg[2] ; ISA_A[16] ;
; N/A ; None ; 1.297 ns ; ISA_D[4] ; DATA_reg[4] ; ISA_A[13] ;
; N/A ; None ; 1.293 ns ; ISA_D[4] ; DATA_reg[4] ; ISA_A[14] ;
; N/A ; None ; 1.259 ns ; ISA_D[1] ; DATA_reg[1] ; ISA_A[16] ;
; N/A ; None ; 1.248 ns ; ISA_D[7] ; DATA_reg[7] ; ISA_A[19] ;
; N/A ; None ; 1.235 ns ; ISA_D[4] ; DATA_reg[4] ; ISA_A[18] ;
; N/A ; None ; 1.233 ns ; ISA_D[0] ; DATA_reg[0] ; ISA_A[16] ;
; N/A ; None ; 1.117 ns ; ISA_D[2] ; DATA_reg[2] ; ISA_A[15] ;
; N/A ; None ; 1.107 ns ; ISA_D[4] ; DATA_reg[4] ; ISA_A[16] ;
; N/A ; None ; 1.100 ns ; ISA_D[5] ; DATA_reg[5] ; ISA_A[6] ;
; N/A ; None ; 1.076 ns ; ISA_D[1] ; DATA_reg[1] ; ISA_A[15] ;
; N/A ; None ; 1.058 ns ; ISA_D[7] ; DATA_reg[7] ; ISA_A[10] ;
; N/A ; None ; 1.050 ns ; ISA_D[0] ; DATA_reg[0] ; ISA_A[15] ;
; N/A ; None ; 1.037 ns ; ISA_D[5] ; DATA_reg[5] ; ISA_A[5] ;
; N/A ; None ; 0.924 ns ; ISA_D[4] ; DATA_reg[4] ; ISA_A[15] ;
; N/A ; None ; 0.888 ns ; ISA_D[2] ; DATA_reg[2] ; ISA_A[6] ;
; N/A ; None ; 0.876 ns ; ISA_D[7] ; DATA_reg[7] ; ISA_A[17] ;
; N/A ; None ; 0.858 ns ; ISA_D[7] ; DATA_reg[7] ; ISA_A[11] ;
; N/A ; None ; 0.847 ns ; ISA_D[1] ; DATA_reg[1] ; ISA_A[6] ;
; N/A ; None ; 0.825 ns ; ISA_D[7] ; DATA_reg[7] ; ISA_A[7] ;
; N/A ; None ; 0.825 ns ; ISA_D[2] ; DATA_reg[2] ; ISA_A[5] ;
; N/A ; None ; 0.821 ns ; ISA_D[0] ; DATA_reg[0] ; ISA_A[6] ;
; N/A ; None ; 0.784 ns ; ISA_D[1] ; DATA_reg[1] ; ISA_A[5] ;
; N/A ; None ; 0.758 ns ; ISA_D[0] ; DATA_reg[0] ; ISA_A[5] ;
; N/A ; None ; 0.731 ns ; ISA_D[7] ; DATA_reg[7] ; ISA_A[13] ;
; N/A ; None ; 0.727 ns ; ISA_D[7] ; DATA_reg[7] ; ISA_A[14] ;
; N/A ; None ; 0.695 ns ; ISA_D[4] ; DATA_reg[4] ; ISA_A[6] ;
; N/A ; None ; 0.669 ns ; ISA_D[7] ; DATA_reg[7] ; ISA_A[18] ;
; N/A ; None ; 0.646 ns ; ISA_D[6] ; DATA_reg[6] ; ISA_A[1] ;
; N/A ; None ; 0.645 ns ; ISA_D[3] ; DATA_reg[3] ; ISA_A[1] ;
; N/A ; None ; 0.635 ns ; ISA_D[6] ; DATA_reg[6] ; ISA_A[0] ;
; N/A ; None ; 0.634 ns ; ISA_D[3] ; DATA_reg[3] ; ISA_A[0] ;
; N/A ; None ; 0.632 ns ; ISA_D[4] ; DATA_reg[4] ; ISA_A[5] ;
; N/A ; None ; 0.541 ns ; ISA_D[7] ; DATA_reg[7] ; ISA_A[16] ;
; N/A ; None ; 0.449 ns ; ISA_D[6] ; DATA_reg[6] ; ISA_IOW ;
; N/A ; None ; 0.448 ns ; ISA_D[3] ; DATA_reg[3] ; ISA_IOW ;
; N/A ; None ; 0.402 ns ; ISA_D[6] ; DATA_reg[6] ; ISA_A[12] ;
; N/A ; None ; 0.401 ns ; ISA_D[3] ; DATA_reg[3] ; ISA_A[12] ;
; N/A ; None ; 0.359 ns ; ISA_D[5] ; DATA_reg[5] ; ISA_A[1] ;
; N/A ; None ; 0.358 ns ; ISA_D[7] ; DATA_reg[7] ; ISA_A[15] ;
; N/A ; None ; 0.348 ns ; ISA_D[5] ; DATA_reg[5] ; ISA_A[0] ;
; N/A ; None ; 0.162 ns ; ISA_D[5] ; DATA_reg[5] ; ISA_IOW ;
; N/A ; None ; 0.147 ns ; ISA_D[2] ; DATA_reg[2] ; ISA_A[1] ;
; N/A ; None ; 0.136 ns ; ISA_D[2] ; DATA_reg[2] ; ISA_A[0] ;
; N/A ; None ; 0.129 ns ; ISA_D[7] ; DATA_reg[7] ; ISA_A[6] ;
; N/A ; None ; 0.115 ns ; ISA_D[5] ; DATA_reg[5] ; ISA_A[12] ;
; N/A ; None ; 0.106 ns ; ISA_D[1] ; DATA_reg[1] ; ISA_A[1] ;
; N/A ; None ; 0.095 ns ; ISA_D[1] ; DATA_reg[1] ; ISA_A[0] ;
; N/A ; None ; 0.080 ns ; ISA_D[0] ; DATA_reg[0] ; ISA_A[1] ;
; N/A ; None ; 0.069 ns ; ISA_D[0] ; DATA_reg[0] ; ISA_A[0] ;
; N/A ; None ; 0.066 ns ; ISA_D[7] ; DATA_reg[7] ; ISA_A[5] ;
; N/A ; None ; -0.046 ns ; ISA_D[4] ; DATA_reg[4] ; ISA_A[1] ;
; N/A ; None ; -0.050 ns ; ISA_D[2] ; DATA_reg[2] ; ISA_IOW ;
; N/A ; None ; -0.057 ns ; ISA_D[4] ; DATA_reg[4] ; ISA_A[0] ;
; N/A ; None ; -0.091 ns ; ISA_D[1] ; DATA_reg[1] ; ISA_IOW ;
; N/A ; None ; -0.097 ns ; ISA_D[2] ; DATA_reg[2] ; ISA_A[12] ;
; N/A ; None ; -0.117 ns ; ISA_D[0] ; DATA_reg[0] ; ISA_IOW ;
; N/A ; None ; -0.138 ns ; ISA_D[1] ; DATA_reg[1] ; ISA_A[12] ;
; N/A ; None ; -0.164 ns ; ISA_D[0] ; DATA_reg[0] ; ISA_A[12] ;
; N/A ; None ; -0.243 ns ; ISA_D[4] ; DATA_reg[4] ; ISA_IOW ;
; N/A ; None ; -0.290 ns ; ISA_D[4] ; DATA_reg[4] ; ISA_A[12] ;
; N/A ; None ; -0.612 ns ; ISA_D[7] ; DATA_reg[7] ; ISA_A[1] ;
; N/A ; None ; -0.623 ns ; ISA_D[7] ; DATA_reg[7] ; ISA_A[0] ;
; N/A ; None ; -0.809 ns ; ISA_D[7] ; DATA_reg[7] ; ISA_IOW ;
; N/A ; None ; -0.856 ns ; ISA_D[7] ; DATA_reg[7] ; ISA_A[12] ;
+---------------+-------------+-----------+----------+-------------+-----------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 5.1 Build 176 10/26/2005 SJ Web Edition
Info: Processing started: Fri Nov 04 15:13:59 2005
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off isa_lpt -c isa_lpt --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "ISA_A[0]" is an undefined clock
Info: Assuming node "ISA_A[1]" is an undefined clock
Info: Assuming node "ISA_AEN" is an undefined clock
Info: Assuming node "ISA_A[3]" is an undefined clock
Info: Assuming node "ISA_A[14]" is an undefined clock
Info: Assuming node "ISA_A[8]" is an undefined clock
Info: Assuming node "ISA_A[19]" is an undefined clock
Info: Assuming node "ISA_A[9]" is an undefined clock
Info: Assuming node "ISA_A[13]" is an undefined clock
Info: Assuming node "ISA_A[16]" is an undefined clock
Info: Assuming node "ISA_A[10]" is an undefined clock
Info: Assuming node "ISA_A[2]" is an undefined clock
Info: Assuming node "ISA_A[4]" is an undefined clock
Info: Assuming node "ISA_A[18]" is an undefined clock
Info: Assuming node "ISA_A[17]" is an undefined clock
Info: Assuming node "ISA_A[11]" is an undefined clock
Info: Assuming node "ISA_A[15]" is an undefined clock
Info: Assuming node "ISA_A[7]" is an undefined clock
Info: Assuming node "ISA_A[6]" is an undefined clock
Info: Assuming node "ISA_A[12]" is an undefined clock
Info: Assuming node "ISA_A[5]" is an undefined clock
Info: Assuming node "ISA_IOW" is an undefined clock
Warning: Found 6 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
Info: Detected gated clock "LPT_DATA_CS~1" as buffer
Info: Detected gated clock "LPT_ACK_CS~158" as buffer
Info: Detected gated clock "LPT_ACK_CS~156" as buffer
Info: Detected gated clock "LPT_ACK_CS~155" as buffer
Info: Detected gated clock "LPT_ACK_CS~154" as buffer
Info: Detected gated clock "LPT_ACK_CS~153" as buffer
Info: No valid register-to-register data paths exist for clock "ISA_A[0]"
Info: No valid register-to-register data paths exist for clock "ISA_A[1]"
Info: No valid register-to-register data paths exist for clock "ISA_AEN"
Info: No valid register-to-register data paths exist for clock "ISA_A[3]"
Info: No valid register-to-register data paths exist for clock "ISA_A[14]"
Info: No valid register-to-register data paths exist for clock "ISA_A[8]"
Info: No valid register-to-register data paths exist for clock "ISA_A[19]"
Info: No valid register-to-register data paths exist for clock "ISA_A[9]"
Info: No valid register-to-register data paths exist for clock "ISA_A[13]"
Info: No valid register-to-register data paths exist for clock "ISA_A[16]"
Info: No valid register-to-register data paths exist for clock "ISA_A[10]"
Info: No valid register-to-register data paths exist for clock "ISA_A[2]"
Info: No valid register-to-register data paths exist for clock "ISA_A[4]"
Info: No valid register-to-register data paths exist for clock "ISA_A[18]"
Info: No valid register-to-register data paths exist for clock "ISA_A[17]"
Info: No valid register-to-register data paths exist for clock "ISA_A[11]"
Info: No valid register-to-register data paths exist for clock "ISA_A[15]"
Info: No valid register-to-register data paths exist for clock "ISA_A[7]"
Info: No valid register-to-register data paths exist for clock "ISA_A[6]"
Info: No valid register-to-register data paths exist for clock "ISA_A[12]"
Info: No valid register-to-register data paths exist for clock "ISA_A[5]"
Info: No valid register-to-register data paths exist for clock "ISA_IOW"
Info: tsu for register "DATA_reg[7]" (data pin = "ISA_D[7]", clock pin = "ISA_A[12]") is 1.122 ns
Info: + Longest pin to register delay is 8.256 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_73; Fanout = 1; PIN Node = 'ISA_D[7]'
Info: 2: + IC(0.000 ns) + CELL(0.955 ns) = 0.955 ns; Loc. = IOC_X28_Y1_N1; Fanout = 1; COMB Node = 'ISA_D[7]~0'
Info: 3: + IC(6.987 ns) + CELL(0.206 ns) = 8.148 ns; Loc. = LCCOMB_X5_Y11_N20; Fanout = 1; COMB Node = 'DATA_reg[7]~feeder'
Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 8.256 ns; Loc. = LCFF_X5_Y11_N21; Fanout = 1; REG Node = 'DATA_reg[7]'
Info: Total cell delay = 1.269 ns ( 15.37 % )
Info: Total interconnect delay = 6.987 ns ( 84.63 % )
Info: + Micro setup delay of destination is -0.040 ns
Info: - Shortest clock path from clock "ISA_A[12]" to destination register is 7.094 ns
Info: 1: + IC(0.000 ns) + CELL(0.944 ns) = 0.944 ns; Loc. = PIN_141; Fanout = 1; CLK Node = 'ISA_A[12]'
Info: 2: + IC(1.725 ns) + CELL(0.370 ns) = 3.039 ns; Loc. = LCCOMB_X5_Y13_N4; Fanout = 4; COMB Node = 'LPT_ACK_CS~158'
Info: 3: + IC(0.384 ns) + CELL(0.366 ns) = 3.789 ns; Loc. = LCCOMB_X5_Y13_N18; Fanout = 1; COMB Node = 'LPT_DATA_CS~1'
Info: 4: + IC(1.794 ns) + CELL(0.000 ns) = 5.583 ns; Loc. = CLKCTRL_G1; Fanout = 8; COMB Node = 'LPT_DATA_CS~1clkctrl'
Info: 5: + IC(0.845 ns) + CELL(0.666 ns) = 7.094 ns; Loc. = LCFF_X5_Y11_N21; Fanout = 1; REG Node = 'DATA_reg[7]'
Info: Total cell delay = 2.346 ns ( 33.07 % )
Info: Total interconnect delay = 4.748 ns ( 66.93 % )
Info: tco from clock "ISA_A[3]" to destination pin "LPT_D[5]" through register "DATA_reg[5]" is 17.222 ns
Info: + Longest clock path from clock "ISA_A[3]" to source register is 10.064 ns
Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_115; Fanout = 1; CLK Node = 'ISA_A[3]'
Info: 2: + IC(2.503 ns) + CELL(0.571 ns) = 4.008 ns; Loc. = LCCOMB_X5_Y13_N10; Fanout = 1; COMB Node = 'LPT_ACK_CS~153'
Info: 3: + IC(0.393 ns) + CELL(0.614 ns) = 5.015 ns; Loc. = LCCOMB_X5_Y13_N24; Fanout = 1; COMB Node = 'LPT_ACK_CS~157'
Info: 4: + IC(0.393 ns) + CELL(0.604 ns) = 6.012 ns; Loc. = LCCOMB_X5_Y13_N4; Fanout = 4; COMB Node = 'LPT_ACK_CS~158'
Info: 5: + IC(0.384 ns) + CELL(0.366 ns) = 6.762 ns; Loc. = LCCOMB_X5_Y13_N18; Fanout = 1; COMB Node = 'LPT_DATA_CS~1'
Info: 6: + IC(1.794 ns) + CELL(0.000 ns) = 8.556 ns; Loc. = CLKCTRL_G1; Fanout = 8; COMB Node = 'LPT_DATA_CS~1clkctrl'
Info: 7: + IC(0.842 ns) + CELL(0.666 ns) = 10.064 ns; Loc. = LCFF_X26_Y4_N1; Fanout = 1; REG Node = 'DATA_reg[5]'
Info: Total cell delay = 3.755 ns ( 37.31 % )
Info: Total interconnect delay = 6.309 ns ( 62.69 % )
Info: + Micro clock to output delay of source is 0.304 ns
Info: + Longest register to pin delay is 6.854 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X26_Y4_N1; Fanout = 1; REG Node = 'DATA_reg[5]'
Info: 2: + IC(3.634 ns) + CELL(3.220 ns)⌨️ 快捷键说明
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