📄 isa_lpt.fit.qmsg
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{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Warning" "WDAT_PRELIMINARY_TIMING" "EP2C5T144C8 " "Warning: Timing characteristics of device EP2C5T144C8 are preliminary" { } { } 0 0 "Timing characteristics of device %1!s! are preliminary" 0 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "28 " "Warning: Found 28 output pins without output pin load capacitance assignment" { { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "LPT_RESET 0 " "Warning: Pin \"LPT_RESET\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "LPT_STOB 0 " "Warning: Pin \"LPT_STOB\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "LPT_D\[0\] 0 " "Warning: Pin \"LPT_D\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "LPT_D\[1\] 0 " "Warning: Pin \"LPT_D\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "LPT_D\[2\] 0 " "Warning: Pin \"LPT_D\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "LPT_D\[3\] 0 " "Warning: Pin \"LPT_D\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "LPT_D\[4\] 0 " "Warning: Pin \"LPT_D\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "LPT_D\[5\] 0 " "Warning: Pin \"LPT_D\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "LPT_D\[6\] 0 " "Warning: Pin \"LPT_D\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "LPT_D\[7\] 0 " "Warning: Pin \"LPT_D\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "DIR0 0 " "Warning: Pin \"DIR0\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "DIR8 0 " "Warning: Pin \"DIR8\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "DIR16 0 " "Warning: Pin \"DIR16\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "a0 0 " "Warning: Pin \"a0\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "a1 0 " "Warning: Pin \"a1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "a2 0 " "Warning: Pin \"a2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "a3 0 " "Warning: Pin \"a3\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "a4 0 " "Warning: Pin \"a4\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "a5 0 " "Warning: Pin \"a5\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "ISA_D\[0\] 0 " "Warning: Pin \"ISA_D\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "ISA_D\[1\] 0 " "Warning: Pin \"ISA_D\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "ISA_D\[2\] 0 " "Warning: Pin \"ISA_D\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "ISA_D\[3\] 0 " "Warning: Pin \"ISA_D\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "ISA_D\[4\] 0 " "Warning: Pin \"ISA_D\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "ISA_D\[5\] 0 " "Warning: Pin \"ISA_D\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "ISA_D\[6\] 0 " "Warning: Pin \"ISA_D\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "ISA_D\[7\] 0 " "Warning: Pin \"ISA_D\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "ISA_READY 0 " "Warning: Pin \"ISA_READY\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE" "7 " "Warning: Following 7 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "ISA_D\[2\] a permanently disabled " "Info: Pin ISA_D\[2\] has a permanently disabled output enable" { } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 13 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "ISA_D\[2\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "isa_lpt" "UNKNOWN" "V1" "D:/evoc/lptb/db/isa_lpt.quartus_db" { Floorplan "D:/evoc/lptb/" "" "" { ISA_D[2] } "NODE_NAME" } "" } } { "D:/evoc/lptb/isa_lpt.fld" "" { Floorplan "D:/evoc/lptb/isa_lpt.fld" "" "" { ISA_D[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "ISA_D\[3\] a permanently disabled " "Info: Pin ISA_D\[3\] has a permanently disabled output enable" { } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 13 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "ISA_D\[3\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "isa_lpt" "UNKNOWN" "V1" "D:/evoc/lptb/db/isa_lpt.quartus_db" { Floorplan "D:/evoc/lptb/" "" "" { ISA_D[3] } "NODE_NAME" } "" } } { "D:/evoc/lptb/isa_lpt.fld" "" { Floorplan "D:/evoc/lptb/isa_lpt.fld" "" "" { ISA_D[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "ISA_D\[4\] a permanently disabled " "Info: Pin ISA_D\[4\] has a permanently disabled output enable" { } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 13 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "ISA_D\[4\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "isa_lpt" "UNKNOWN" "V1" "D:/evoc/lptb/db/isa_lpt.quartus_db" { Floorplan "D:/evoc/lptb/" "" "" { ISA_D[4] } "NODE_NAME" } "" } } { "D:/evoc/lptb/isa_lpt.fld" "" { Floorplan "D:/evoc/lptb/isa_lpt.fld" "" "" { ISA_D[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "ISA_D\[5\] a permanently disabled " "Info: Pin ISA_D\[5\] has a permanently disabled output enable" { } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 13 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "ISA_D\[5\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "isa_lpt" "UNKNOWN" "V1" "D:/evoc/lptb/db/isa_lpt.quartus_db" { Floorplan "D:/evoc/lptb/" "" "" { ISA_D[5] } "NODE_NAME" } "" } } { "D:/evoc/lptb/isa_lpt.fld" "" { Floorplan "D:/evoc/lptb/isa_lpt.fld" "" "" { ISA_D[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "ISA_D\[6\] a permanently disabled " "Info: Pin ISA_D\[6\] has a permanently disabled output enable" { } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 13 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "ISA_D\[6\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "isa_lpt" "UNKNOWN" "V1" "D:/evoc/lptb/db/isa_lpt.quartus_db" { Floorplan "D:/evoc/lptb/" "" "" { ISA_D[6] } "NODE_NAME" } "" } } { "D:/evoc/lptb/isa_lpt.fld" "" { Floorplan "D:/evoc/lptb/isa_lpt.fld" "" "" { ISA_D[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "ISA_D\[7\] a permanently disabled " "Info: Pin ISA_D\[7\] has a permanently disabled output enable" { } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 13 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "ISA_D\[7\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "isa_lpt" "UNKNOWN" "V1" "D:/evoc/lptb/db/isa_lpt.quartus_db" { Floorplan "D:/evoc/lptb/" "" "" { ISA_D[7] } "NODE_NAME" } "" } } { "D:/evoc/lptb/isa_lpt.fld" "" { Floorplan "D:/evoc/lptb/isa_lpt.fld" "" "" { ISA_D[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "ISA_READY a permanently disabled " "Info: Pin ISA_READY has a permanently disabled output enable" { } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 19 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "ISA_READY" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "isa_lpt" "UNKNOWN" "V1" "D:/evoc/lptb/db/isa_lpt.quartus_db" { Floorplan "D:/evoc/lptb/" "" "" { ISA_READY } "NODE_NAME" } "" } } { "D:/evoc/lptb/isa_lpt.fld" "" { Floorplan "D:/evoc/lptb/isa_lpt.fld" "" "" { ISA_READY } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} } { } 0 0 "Following %1!d! pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" 0 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "17 " "Warning: Following 17 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LPT_RESET GND " "Info: Pin LPT_RESET has GND driving its datain port" { } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 22 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LPT_RESET" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "isa_lpt" "UNKNOWN" "V1" "D:/evoc/lptb/db/isa_lpt.quartus_db" { Floorplan "D:/evoc/lptb/" "" "" { LPT_RESET } "NODE_NAME" } "" } } { "D:/evoc/lptb/isa_lpt.fld" "" { Floorplan "D:/evoc/lptb/isa_lpt.fld" "" "" { LPT_RESET } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DIR0 GND " "Info: Pin DIR0 has GND driving its datain port" { } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 27 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "DIR0" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "isa_lpt" "UNKNOWN" "V1" "D:/evoc/lptb/db/isa_lpt.quartus_db" { Floorplan "D:/evoc/lptb/" "" "" { DIR0 } "NODE_NAME" } "" } } { "D:/evoc/lptb/isa_lpt.fld" "" { Floorplan "D:/evoc/lptb/isa_lpt.fld" "" "" { DIR0 } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DIR8 VCC " "Info: Pin DIR8 has VCC driving its datain port" { } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 28 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "DIR8" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "isa_lpt" "UNKNOWN" "V1" "D:/evoc/lptb/db/isa_lpt.quartus_db" { Floorplan "D:/evoc/lptb/" "" "" { DIR8 } "NODE_NAME" } "" } } { "D:/evoc/lptb/isa_lpt.fld" "" { Floorplan "D:/evoc/lptb/isa_lpt.fld" "" "" { DIR8 } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DIR16 GND " "Info: Pin DIR16 has GND driving its datain port" { } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 29 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "DIR16" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "isa_lpt" "UNKNOWN" "V1" "D:/evoc/lptb/db/isa_lpt.quartus_db" { Floorplan "D:/evoc/lptb/" "" "" { DIR16 } "NODE_NAME" } "" } } { "D:/evoc/lptb/isa_lpt.fld" "" { Floorplan "D:/evoc/lptb/isa_lpt.fld" "" "" { DIR16 } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "a0 GND " "Info: Pin a0 has GND driving its datain port" { } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 30 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "a0" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "isa_lpt" "UNKNOWN" "V1" "D:/evoc/lptb/db/isa_lpt.quartus_db" { Floorplan "D:/evoc/lptb/" "" "" { a0 } "NODE_NAME" } "" } } { "D:/evoc/lptb/isa_lpt.fld" "" { Floorplan "D:/evoc/lptb/isa_lpt.fld" "" "" { a0 } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "a1 GND " "Info: Pin a1 has GND driving its datain port" { } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 31 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "a1" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "isa_lpt" "UNKNOWN" "V1" "D:/evoc/lptb/db/isa_lpt.quartus_db" { Floorplan "D:/evoc/lptb/" "" "" { a1 } "NODE_NAME" } "" } } { "D:/evoc/lptb/isa_lpt.fld" "" { Floorplan "D:/evoc/lptb/isa_lpt.fld" "" "" { a1 } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "a2 GND " "Info: Pin a2 has GND driving its datain port" { } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 32 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "a2" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "isa_lpt" "UNKNOWN" "V1" "D:/evoc/lptb/db/isa_lpt.quartus_db" { Floorplan "D:/evoc/lptb/" "" "" { a2 } "NODE_NAME" } "" } } { "D:/evoc/lptb/isa_lpt.fld" "" { Floorplan "D:/evoc/lptb/isa_lpt.fld" "" "" { a2 } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "a3 GND " "Info: Pin a3 has GND driving its datain port" { } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 33 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "a3" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "isa_lpt" "UNKNOWN" "V1" "D:/evoc/lptb/db/isa_lpt.quartus_db" { Floorplan "D:/evoc/lptb/" "" "" { a3 } "NODE_NAME" } "" } } { "D:/evoc/lptb/isa_lpt.fld" "" { Floorplan "D:/evoc/lptb/isa_lpt.fld" "" "" { a3 } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "a4 GND " "Info: Pin a4 has GND driving its datain port" { } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 34 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "a4" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "isa_lpt" "UNKNOWN" "V1" "D:/evoc/lptb/db/isa_lpt.quartus_db" { Floorplan "D:/evoc/lptb/" "" "" { a4 } "NODE_NAME" } "" } } { "D:/evoc/lptb/isa_lpt.fld" "" { Floorplan "D:/evoc/lptb/isa_lpt.fld" "" "" { a4 } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "a5 GND " "Info: Pin a5 has GND driving its datain port" { } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 35 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "a5" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "isa_lpt" "UNKNOWN" "V1" "D:/evoc/lptb/db/isa_lpt.quartus_db" { Floorplan "D:/evoc/lptb/" "" "" { a5 } "NODE_NAME" } "" } } { "D:/evoc/lptb/isa_lpt.fld" "" { Floorplan "D:/evoc/lptb/isa_lpt.fld" "" "" { a5 } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ISA_D\[2\] VCC " "Info: Pin ISA_D\[2\] has VCC driving its datain port" { } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 13 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "ISA_D\[2\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "isa_lpt" "UNKNOWN" "V1" "D:/evoc/lptb/db/isa_lpt.quartus_db" { Floorplan "D:/evoc/lptb/" "" "" { ISA_D[2] } "NODE_NAME" } "" } } { "D:/evoc/lptb/isa_lpt.fld" "" { Floorplan "D:/evoc/lptb/isa_lpt.fld" "" "" { ISA_D[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ISA_D\[3\] VCC " "Info: Pin ISA_D\[3\] has VCC driving its datain port" { } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 13 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "ISA_D\[3\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "isa_lpt" "UNKNOWN" "V1" "D:/evoc/lptb/db/isa_lpt.quartus_db" { Floorplan "D:/evoc/lptb/" "" "" { ISA_D[3] } "NODE_NAME" } "" } } { "D:/evoc/lptb/isa_lpt.fld" "" { Floorplan "D:/evoc/lptb/isa_lpt.fld" "" "" { ISA_D[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ISA_D\[4\] VCC " "Info: Pin ISA_D\[4\] has VCC driving its datain port" { } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 13 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "ISA_D\[4\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "isa_lpt" "UNKNOWN" "V1" "D:/evoc/lptb/db/isa_lpt.quartus_db" { Floorplan "D:/evoc/lptb/" "" "" { ISA_D[4] } "NODE_NAME" } "" } } { "D:/evoc/lptb/isa_lpt.fld" "" { Floorplan "D:/evoc/lptb/isa_lpt.fld" "" "" { ISA_D[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ISA_D\[5\] VCC " "Info: Pin ISA_D\[5\] has VCC driving its datain port" { } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 13 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "ISA_D\[5\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "isa_lpt" "UNKNOWN" "V1" "D:/evoc/lptb/db/isa_lpt.quartus_db" { Floorplan "D:/evoc/lptb/" "" "" { ISA_D[5] } "NODE_NAME" } "" } } { "D:/evoc/lptb/isa_lpt.fld" "" { Floorplan "D:/evoc/lptb/isa_lpt.fld" "" "" { ISA_D[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ISA_D\[6\] VCC " "Info: Pin ISA_D\[6\] has VCC driving its datain port" { } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 13 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "ISA_D\[6\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "isa_lpt" "UNKNOWN" "V1" "D:/evoc/lptb/db/isa_lpt.quartus_db" { Floorplan "D:/evoc/lptb/" "" "" { ISA_D[6] } "NODE_NAME" } "" } } { "D:/evoc/lptb/isa_lpt.fld" "" { Floorplan "D:/evoc/lptb/isa_lpt.fld" "" "" { ISA_D[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ISA_D\[7\] VCC " "Info: Pin ISA_D\[7\] has VCC driving its datain port" { } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 13 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "ISA_D\[7\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "isa_lpt" "UNKNOWN" "V1" "D:/evoc/lptb/db/isa_lpt.quartus_db" { Floorplan "D:/evoc/lptb/" "" "" { ISA_D[7] } "NODE_NAME" } "" } } { "D:/evoc/lptb/isa_lpt.fld" "" { Floorplan "D:/evoc/lptb/isa_lpt.fld" "" "" { ISA_D[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ISA_READY VCC " "Info: Pin ISA_READY has VCC driving its datain port" { } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 19 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "ISA_READY" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "isa_lpt" "UNKNOWN" "V1" "D:/evoc/lptb/db/isa_lpt.quartus_db" { Floorplan "D:/evoc/lptb/" "" "" { ISA_READY } "NODE_NAME" } "" } } { "D:/evoc/lptb/isa_lpt.fld" "" { Floorplan "D:/evoc/lptb/isa_lpt.fld" "" "" { ISA_READY } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0}
{ "Info" "IFSAC_FSAC_ALL_OUTPUT_ENABLE_GROUPS" "" "Info: Following groups of pins have the same output enable" { { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP" "LPT_BUSY_CS " "Info: Following pins have the same output enable: LPT_BUSY_CS" { { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional ISA_D\[0\] LVTTL " "Info: Type bidirectional pin ISA_D\[0\] uses the LVTTL I/O standard" { } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 13 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "ISA_D\[0\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "isa_lpt" "UNKNOWN" "V1" "D:/evoc/lptb/db/isa_lpt.quartus_db" { Floorplan "D:/evoc/lptb/" "" "" { ISA_D[0] } "NODE_NAME" } "" } } { "D:/evoc/lptb/isa_lpt.fld" "" { Floorplan "D:/evoc/lptb/isa_lpt.fld" "" "" { ISA_D[0] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} } { } 0 0 "Following pins have the same output enable: %1!s!" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP" "LPT_ACK_CS " "Info: Following pins have the same output enable: LPT_ACK_CS" { { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional ISA_D\[1\] LVTTL " "Info: Type bidirectional pin ISA_D\[1\] uses the LVTTL I/O standard" { } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 13 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "ISA_D\[1\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "isa_lpt" "UNKNOWN" "V1" "D:/evoc/lptb/db/isa_lpt.quartus_db" { Floorplan "D:/evoc/lptb/" "" "" { ISA_D[1] } "NODE_NAME" } "" } } { "D:/evoc/lptb/isa_lpt.fld" "" { Floorplan "D:/evoc/lptb/isa_lpt.fld" "" "" { ISA_D[1] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} } { } 0 0 "Following pins have the same output enable: %1!s!" 0 0} } { } 0 0 "Following groups of pins have the same output enable" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 37 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 37 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 04 15:13:49 2005 " "Info: Processing ended: Fri Nov 04 15:13:49 2005" { } { } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Info: Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
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