isa_lpt.fit.qmsg

这也是8255的设计,不知道是否好使,希望得到验证

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Web Edition " "Info: Version 5.1 Build 176 10/26/2005 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 04 15:13:42 2005 " "Info: Processing started: Fri Nov 04 15:13:42 2005" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off isa_lpt -c isa_lpt " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off isa_lpt -c isa_lpt" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "isa_lpt EP2C5T144C8 " "Info: Selected device EP2C5T144C8 for design \"isa_lpt\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0}  } {  } 0 0 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5T144I8 " "Info: Device EP2C5T144I8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8T144C8 " "Info: Device EP2C8T144C8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8T144I8 " "Info: Device EP2C8T144I8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "3 54 " "Info: No exact pin location assignment(s) for 3 pins of 54 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "DIR0 " "Info: Pin DIR0 not assigned to an exact location on the device" {  } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 27 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "DIR0" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "isa_lpt" "UNKNOWN" "V1" "D:/evoc/lptb/db/isa_lpt.quartus_db" { Floorplan "D:/evoc/lptb/" "" "" { DIR0 } "NODE_NAME" } "" } } { "D:/evoc/lptb/isa_lpt.fld" "" { Floorplan "D:/evoc/lptb/isa_lpt.fld" "" "" { DIR0 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "DIR8 " "Info: Pin DIR8 not assigned to an exact location on the device" {  } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 28 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "DIR8" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "isa_lpt" "UNKNOWN" "V1" "D:/evoc/lptb/db/isa_lpt.quartus_db" { Floorplan "D:/evoc/lptb/" "" "" { DIR8 } "NODE_NAME" } "" } } { "D:/evoc/lptb/isa_lpt.fld" "" { Floorplan "D:/evoc/lptb/isa_lpt.fld" "" "" { DIR8 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "DIR16 " "Info: Pin DIR16 not assigned to an exact location on the device" {  } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 29 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "DIR16" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "isa_lpt" "UNKNOWN" "V1" "D:/evoc/lptb/db/isa_lpt.quartus_db" { Floorplan "D:/evoc/lptb/" "" "" { DIR16 } "NODE_NAME" } "" } } { "D:/evoc/lptb/isa_lpt.fld" "" { Floorplan "D:/evoc/lptb/isa_lpt.fld" "" "" { DIR16 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0}  } {  } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "LPT_DATA_CS~1  " "Info: Automatically promoted node LPT_DATA_CS~1 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0}  } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 40 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LPT_DATA_CS~1" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "isa_lpt" "UNKNOWN" "V1" "D:/evoc/lptb/db/isa_lpt.quartus_db" { Floorplan "D:/evoc/lptb/" "" "" { LPT_DATA_CS~1 } "NODE_NAME" } "" } } { "D:/evoc/lptb/isa_lpt.fld" "" { Floorplan "D:/evoc/lptb/isa_lpt.fld" "" "" { LPT_DATA_CS~1 } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0}