isa_lpt.map.rpt

这也是8255的设计,不知道是否好使,希望得到验证

; Retiming Meta-Stability Register Sequence Length                   ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
+--------------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                     ;
+----------------------------------+-----------------+------------------------+------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------+------------------------------+
; isa_lpt.v                        ; yes             ; User Verilog HDL File  ; D:/evoc/lptb/isa_lpt.v       ;
+----------------------------------+-----------------+------------------------+------------------------------+


+-------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                 ;
+---------------------------------------------+---------------+
; Resource                                    ; Usage         ;
+---------------------------------------------+---------------+
; Total combinational functions               ; 10            ;
; Logic element usage by number of LUT inputs ;               ;
;     -- 4 input functions                    ; 10            ;
;     -- 3 input functions                    ; 0             ;
;     -- <=2 input functions                  ; 0             ;
;         -- Combinational cells for routing  ; 0             ;
; Logic elements by mode                      ;               ;
;     -- normal mode                          ; 10            ;
;     -- arithmetic mode                      ; 0             ;
; Total registers                             ; 8             ;
; I/O pins                                    ; 54            ;
; Maximum fan-out node                        ; LPT_DATA_CS~1 ;
; Maximum fan-out                             ; 8             ;
; Total fan-out                               ; 69            ;
; Average fan-out                             ; 0.96          ;
+---------------------------------------------+---------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                          ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+
; |isa_lpt                   ; 10 (10)           ; 8 (8)        ; 0           ; 0            ; 0       ; 0         ; 54   ; 0            ; |isa_lpt            ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 8     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/evoc/lptb/isa_lpt.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Web Edition
    Info: Processing started: Fri Nov 04 15:13:38 2005
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off isa_lpt -c isa_lpt
Info: Found 1 design units, including 1 entities, in source file isa_lpt.v
    Info: Found entity 1: isa_lpt
Info: Elaborating entity "isa_lpt" for the top level hierarchy
Info (10035): Verilog HDL or VHDL information at isa_lpt.v(17): object "ISA_RESET" declared but not used
Info (10035): Verilog HDL or VHDL information at isa_lpt.v(22): object "LPT_RESET" declared but not used
Warning (10036): Verilog HDL or VHDL warning at isa_lpt.v(39): object "ISA_IOCS16" assigned a value but never read
Warning (10230): Verilog HDL assignment warning at isa_lpt.v(49): truncated value with size 32 to match size of target (1)
Warning (10273): Verilog HDL warning at isa_lpt.v(54): sign extended using "x" or "z"
Warning (10230): Verilog HDL assignment warning at isa_lpt.v(54): truncated value with size 32 to match size of target (1)
Warning (10034): Output port "LPT_RESET" at isa_lpt.v(22) has no driver
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "LPT_RESET" stuck at GND
    Warning: Pin "DIR0" stuck at GND
    Warning: Pin "DIR8" stuck at VCC
    Warning: Pin "DIR16" stuck at GND
    Warning: Pin "a0" stuck at GND
    Warning: Pin "a1" stuck at GND
    Warning: Pin "a2" stuck at GND
    Warning: Pin "a3" stuck at GND
    Warning: Pin "a4" stuck at GND
    Warning: Pin "a5" stuck at GND
Warning: Design contains 1 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "ISA_RESET"
Info: Implemented 72 device resources after synthesis - the final resource count might be different
    Info: Implemented 26 input pins
    Info: Implemented 19 output pins
    Info: Implemented 9 bidirectional pins
    Info: Implemented 18 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 18 warnings
    Info: Processing ended: Fri Nov 04 15:13:39 2005
    Info: Elapsed time: 00:00:02