📄 isa_lpt.tan.talkback.xml
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<!--
This XML file (created on Fri Nov 04 15:14:00 2005) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature. To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder. For more information, go
to www.altera.com/products/software/download/dnl-download_license.html
-->
<talkback>
<ver>5.1</ver>
<schema>quartus_version_5.1_build_176.xsd</schema><license>
<host_id>001125d723d9</host_id>
<nic_id>001125d723d9</nic_id>
<cdrive_id>0009da0f</cdrive_id>
</license>
<tool>
<name>Quartus II</name>
<version>5.1</version>
<build>Build 176</build>
<binary_type>32</binary_type>
<module>quartus_tan.exe</module>
<edition>Web Edition</edition>
<compilation_end_time>Fri Nov 04 15:14:01 2005</compilation_end_time>
</tool>
<machine>
<os>Windows XP</os>
<cpu>
<proc_count>1</proc_count>
<cpu_freq units="MHz">798</cpu_freq>
</cpu>
<ram units="MB">1271</ram>
</machine>
<top_file>D:/evoc/lptb/isa_lpt</top_file>
<mep_data>
<command_line>quartus_tan --read_settings_files=off --write_settings_files=off isa_lpt -c isa_lpt --timing_analysis_only</command_line>
</mep_data>
<software_data>
<smart_recompile>off</smart_recompile>
</software_data>
<clock_settings_summary>
<row>
<clock_node_name>ISA_A[0]</clock_node_name>
<type>User Pin</type>
<fmax_requirement>None</fmax_requirement>
<early_latency units="ns">0.000</early_latency>
<late_latency units="ns">0.000</late_latency>
<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
<divide_base_fmax_by>N/A</divide_base_fmax_by>
<offset>N/A</offset>
</row>
<row>
<clock_node_name>ISA_A[1]</clock_node_name>
<type>User Pin</type>
<fmax_requirement>None</fmax_requirement>
<early_latency units="ns">0.000</early_latency>
<late_latency units="ns">0.000</late_latency>
<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
<divide_base_fmax_by>N/A</divide_base_fmax_by>
<offset>N/A</offset>
</row>
<row>
<clock_node_name>ISA_AEN</clock_node_name>
<type>User Pin</type>
<fmax_requirement>None</fmax_requirement>
<early_latency units="ns">0.000</early_latency>
<late_latency units="ns">0.000</late_latency>
<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
<divide_base_fmax_by>N/A</divide_base_fmax_by>
<offset>N/A</offset>
</row>
<row>
<clock_node_name>ISA_A[3]</clock_node_name>
<type>User Pin</type>
<fmax_requirement>None</fmax_requirement>
<early_latency units="ns">0.000</early_latency>
<late_latency units="ns">0.000</late_latency>
<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
<divide_base_fmax_by>N/A</divide_base_fmax_by>
<offset>N/A</offset>
</row>
<row>
<clock_node_name>ISA_A[14]</clock_node_name>
<type>User Pin</type>
<fmax_requirement>None</fmax_requirement>
<early_latency units="ns">0.000</early_latency>
<late_latency units="ns">0.000</late_latency>
<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
<divide_base_fmax_by>N/A</divide_base_fmax_by>
<offset>N/A</offset>
</row>
<row>
<clock_node_name>ISA_A[8]</clock_node_name>
<type>User Pin</type>
<fmax_requirement>None</fmax_requirement>
<early_latency units="ns">0.000</early_latency>
<late_latency units="ns">0.000</late_latency>
<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
<divide_base_fmax_by>N/A</divide_base_fmax_by>
<offset>N/A</offset>
</row>
<row>
<clock_node_name>ISA_A[19]</clock_node_name>
<type>User Pin</type>
<fmax_requirement>None</fmax_requirement>
<early_latency units="ns">0.000</early_latency>
<late_latency units="ns">0.000</late_latency>
<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
<divide_base_fmax_by>N/A</divide_base_fmax_by>
<offset>N/A</offset>
</row>
<row>
<clock_node_name>ISA_A[9]</clock_node_name>
<type>User Pin</type>
<fmax_requirement>None</fmax_requirement>
<early_latency units="ns">0.000</early_latency>
<late_latency units="ns">0.000</late_latency>
<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
<divide_base_fmax_by>N/A</divide_base_fmax_by>
<offset>N/A</offset>
</row>
<row>
<clock_node_name>ISA_A[13]</clock_node_name>
<type>User Pin</type>
<fmax_requirement>None</fmax_requirement>
<early_latency units="ns">0.000</early_latency>
<late_latency units="ns">0.000</late_latency>
<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
<divide_base_fmax_by>N/A</divide_base_fmax_by>
<offset>N/A</offset>
</row>
<row>
<clock_node_name>ISA_A[16]</clock_node_name>
<type>User Pin</type>
<fmax_requirement>None</fmax_requirement>
<early_latency units="ns">0.000</early_latency>
<late_latency units="ns">0.000</late_latency>
<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
<divide_base_fmax_by>N/A</divide_base_fmax_by>
<offset>N/A</offset>
</row>
<row>
<clock_node_name>ISA_A[10]</clock_node_name>
<type>User Pin</type>
<fmax_requirement>None</fmax_requirement>
<early_latency units="ns">0.000</early_latency>
<late_latency units="ns">0.000</late_latency>
<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
<divide_base_fmax_by>N/A</divide_base_fmax_by>
<offset>N/A</offset>
</row>
<row>
<clock_node_name>ISA_A[2]</clock_node_name>
<type>User Pin</type>
<fmax_requirement>None</fmax_requirement>
<early_latency units="ns">0.000</early_latency>
<late_latency units="ns">0.000</late_latency>
<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
<divide_base_fmax_by>N/A</divide_base_fmax_by>
<offset>N/A</offset>
</row>
<row>
<clock_node_name>ISA_A[4]</clock_node_name>
<type>User Pin</type>
<fmax_requirement>None</fmax_requirement>
<early_latency units="ns">0.000</early_latency>
<late_latency units="ns">0.000</late_latency>
<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
<divide_base_fmax_by>N/A</divide_base_fmax_by>
<offset>N/A</offset>
</row>
<row>
<clock_node_name>ISA_A[18]</clock_node_name>
<type>User Pin</type>
<fmax_requirement>None</fmax_requirement>
<early_latency units="ns">0.000</early_latency>
<late_latency units="ns">0.000</late_latency>
<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
<divide_base_fmax_by>N/A</divide_base_fmax_by>
<offset>N/A</offset>
</row>
<row>
<clock_node_name>ISA_A[17]</clock_node_name>
<type>User Pin</type>
<fmax_requirement>None</fmax_requirement>
<early_latency units="ns">0.000</early_latency>
<late_latency units="ns">0.000</late_latency>
<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
<divide_base_fmax_by>N/A</divide_base_fmax_by>
<offset>N/A</offset>
</row>
<row>
<clock_node_name>ISA_A[11]</clock_node_name>
<type>User Pin</type>
<fmax_requirement>None</fmax_requirement>
<early_latency units="ns">0.000</early_latency>
<late_latency units="ns">0.000</late_latency>
<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
<divide_base_fmax_by>N/A</divide_base_fmax_by>
<offset>N/A</offset>
</row>
<row>
<clock_node_name>ISA_A[15]</clock_node_name>
<type>User Pin</type>
<fmax_requirement>None</fmax_requirement>
<early_latency units="ns">0.000</early_latency>
<late_latency units="ns">0.000</late_latency>
<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
<divide_base_fmax_by>N/A</divide_base_fmax_by>
<offset>N/A</offset>
</row>
<row>
<clock_node_name>ISA_A[7]</clock_node_name>
<type>User Pin</type>
<fmax_requirement>None</fmax_requirement>
<early_latency units="ns">0.000</early_latency>
<late_latency units="ns">0.000</late_latency>
<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
<divide_base_fmax_by>N/A</divide_base_fmax_by>
<offset>N/A</offset>
</row>
<row>
<clock_node_name>ISA_A[6]</clock_node_name>
<type>User Pin</type>
<fmax_requirement>None</fmax_requirement>
<early_latency units="ns">0.000</early_latency>
<late_latency units="ns">0.000</late_latency>
<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
<divide_base_fmax_by>N/A</divide_base_fmax_by>
<offset>N/A</offset>
</row>
<row>
<clock_node_name>ISA_A[12]</clock_node_name>
<type>User Pin</type>
<fmax_requirement>None</fmax_requirement>
<early_latency units="ns">0.000</early_latency>
<late_latency units="ns">0.000</late_latency>
<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
<divide_base_fmax_by>N/A</divide_base_fmax_by>
<offset>N/A</offset>
</row>
<row>
<clock_node_name>ISA_A[5]</clock_node_name>
<type>User Pin</type>
<fmax_requirement>None</fmax_requirement>
<early_latency units="ns">0.000</early_latency>
<late_latency units="ns">0.000</late_latency>
<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
<divide_base_fmax_by>N/A</divide_base_fmax_by>
<offset>N/A</offset>
</row>
<row>
<clock_node_name>ISA_IOW</clock_node_name>
<type>User Pin</type>
<fmax_requirement>None</fmax_requirement>
<early_latency units="ns">0.000</early_latency>
<late_latency units="ns">0.000</late_latency>
<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
<divide_base_fmax_by>N/A</divide_base_fmax_by>
<offset>N/A</offset>
</row>
</clock_settings_summary>
<performance>
<nonclk>
<type>Worst-case tsu</type>
<slack>N/A</slack>
<required>None</required>
<actual>1.122 ns</actual>
</nonclk>
<nonclk>
<type>Worst-case tco</type>
<slack>N/A</slack>
<required>None</required>
<actual>17.222 ns</actual>
</nonclk>
<nonclk>
<type>Worst-case tpd</type>
<slack>N/A</slack>
<required>None</required>
<actual>15.560 ns</actual>
</nonclk>
<nonclk>
<type>Worst-case th</type>
<slack>N/A</slack>
<required>None</required>
<actual>3.375 ns</actual>
</nonclk>
</performance>
<compile_id>9AD787CF</compile_id>
</talkback>
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