📄 adsp-bf533-ez-kit.c
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//------------------------------------------------------------------------------//
// Function: Set_RTC //
// //
// Purpose: Configures the RTC status register RTC_STAT with the appropriate //
// time values as entered by the user. //
// //
// Returns: Will return "true" if user has entered time values out of the //
// acceptable range. //
//------------------------------------------------------------------------------//
char Set_RTC(unsigned int Days, unsigned int Hours, unsigned int Minutes,
unsigned int Seconds)
{
if ((Days < 32767) && (Hours < 24) && (Minutes < 60) && (Seconds < 60))
{
//Declare time and clear it
unsigned int Time = 0;
*pRTC_ISTAT = 0x3FFF; //RTC_ISTAT is write-1 to clear
//"and" days with 0xBFFF to truncate to 15 bits, shift into position and "or" with Time
Time |= ((Days &= 0xBFFF) << 17);
//"and" hours with 0x1F to truncate to 5 bits, shift into position and "or" with Time
Time |= ((Hours &= 0x1F) << 12);
//"and" minutes with 0x3F to truncate to 6 bits, shift into position and "or" with Time
Time |= ((Minutes &= 0x3F) << 6);
//"and" seconds with 0x3F to truncate to 6 bits and "or" with Time
Time |= (Seconds &= 0x3F);
*pRTC_STAT = Time;
while (!(0x4000 & *pRTC_ISTAT))
{
//do nothing
//waiting for Write Complete bit to go high
} //end while
return 0;
} //end if
else
return 1; //Error Warning generated, overload has occurred
} //end Set_RTC
//------------------------------------------------------------------------------//
// Function: Set_RTC_Alarm //
// //
// Purpose: Configures the RTC alarm register RTC_ALARM with the appropriate //
// time values as entered by the user. //
// //
// Returns: Will return "true" if user has entered time values out of the //
// acceptable range. //
//------------------------------------------------------------------------------//
char Set_RTC_Alarm(unsigned int Days, unsigned int Hours, unsigned int Minutes,
unsigned int Seconds)
{
if ((Days < 32767) && (Hours < 24) && (Minutes < 60) && (Seconds < 60))
{
//Declare Alarm and clear it
unsigned int Alarm = 0;
*pRTC_ISTAT = 0x3FFF; //RTC_ISTAT is write-1 to clear
//"and" days with 0xBFFF to truncate to 15 bits, shift into position and "or" with Time
Alarm |= ((Days &= 0xBFFF) << 17);
//"and" hours with 0x1F to truncate to 5 bits, shift into position and "or" with Time
Alarm |= ((Hours &= 0x1F) << 12);
//"and" minutes with 0x3F to truncate to 6 bits, shift into position and "or" with Time
Alarm |= ((Minutes &= 0x3F) << 6);
//"and" seconds with 0x3F to truncate to 6 bits and "or" with Time
Alarm |= (Seconds &= 0x3F);
*pRTC_ALARM = Alarm;
while (!(0x4000 & *pRTC_ISTAT))
{
//do nothing
//waiting for Write Complete bit to go high
} //end while
return 0;
} //end if
else
return 1;
} //end Set_RTC_Alarm
//------------------------------------------------------------------------------//
// Function: Set_RTC_Stopwatch //
// //
// Purpose: Configures the RTC_Stopwatch register RTC_SWCNT with the //
// appropriate time values as entered by the user. //
// //
// Return: Will return true if entered value exceeds the maxmimum count of the //
// stopwatch register. The value can be no larger than 65,536 seconds. //
//------------------------------------------------------------------------------//
char Set_RTC_Stopwatch(unsigned int Hours, unsigned int Minutes, unsigned int Seconds)
{
unsigned int Stopwatch = 0;
Stopwatch = (Seconds + (Minutes * 60) + (Hours * 3600));
if (Stopwatch < 65536)
{
*pRTC_SWCNT = Stopwatch;
return 0;
}
else
return 1; //Error warning, stopwatch count exceeds 65,535
} //end Set_RTC_Stopwatch
//------------------------------------------------------------------------------//
// Function: Set_PLL_DIV //
// //
// Parameters: CSEL (Core Clock Divider Select bits), SSEL (System Select //
// Divider Select Bits) //
// //
// Purpose: Configures the PLL_DIV register with the appropriate divider ratios //
// to set the CCLK and SCLK to the desired values. //
// //
// Returns: Will return "true" if user has entered divider values out of the //
// acceptable range. //
//------------------------------------------------------------------------------//
char Set_PLL_Div(unsigned short CSEL, unsigned short SSEL)
{
if ((CSEL < 5) && (SSEL < 16))
{
*pPLL_DIV = ((CSEL << 4) | SSEL);
return 1;
}
else
return 0; //error, Core Select or System Select values are out of range
}
//------------------------------------------------------------------------------//
// Function: Set_PLL_CTL //
// //
// Parameters: MSEL (VCO Multiplier Select bits), Bypass (PLL Bypass select), //
// PDWN (Power Down), STOPCK (Stop Clock), PLL_OFF, DF (Divide //
// Frequency). //
// //
// Purpose: Configures the fields in the PLL_CTL register. Note: changes will //
// not take place until a specific PLL programing sequence is executed.//
// //
// Returns: Will return 1 if any parameter values are outside the //
// acceptable range. //
//------------------------------------------------------------------------------//
char Set_PLL_CTL(USHORT msel, UCHAR bypass, UCHAR pwdn, UCHAR stopck, UCHAR pll_off, UCHAR df)
{
if ((msel < 64) && (bypass < 2) && (pwdn < 2) && (stopck < 2) && (pll_off < 2) && (df < 2))
{
asm("CLI R2;"); /*disable interrupts, copy IMASK to R2 */
*pPLL_CTL = ((msel << 9) | (bypass << 8) | (pwdn << 5) | (stopck << 3) | (pll_off << 1) | df);
asm("IDLE;"); /*drain pipeline, enter idle state, wait for PLL wake-up */
asm("STI R2;"); /*after PLL wakeup occurs, restore interrupts and IMASK */
return 0;
}
else
return 1; //error, one or more of the values is out of range
}
//------------------------------------------------------------------------------//
// Function: Set_PLL_Frequencies //
// //
// Parameters: CSEL (Core Clock Divider Select bits), SSEL (System Select //
// Divider Select Bits) //
// //
// Purpose: Configures the PLL_DIV register with the appropriate divider ratios //
// to set the CCLK and SCLK to the desired values. //
// //
// Returns: Will return "true" if user has entered divider values out of the //
// acceptable range. //
//------------------------------------------------------------------------------//
USHORT Set_PLL_Frequencies( cPLL_Config * C )
{
USHORT err;
err = Set_PLL_Div( C->csel, C->ssel );
err |= Set_PLL_CTL( C->msel, C->bypass, C->pwdn, C->stopck, C->pll_off, C->df );
return err;
}
cPLL_Config EZKIT_594C_118S = { 0, 5, 22, 0, 0, 0, 0, 0 };
cPLL_Config EZKIT_594C_99S = { 0, 6, 22, 0, 0, 0, 0, 0 };
//------------------------------------------------------------------------------//
// Function: Set_VR_CTL //
// //
// Parameters: WAKE, VLEV, FREQ, GAIN //
// //
// Purpose: Configures fields for the Voltage Regulator Control Register //
// //
// Returns: Will return 1 if any parameter values are outside the //
// acceptable range. //
//------------------------------------------------------------------------------//
char Set_VR_CTL(unsigned short VLEV, unsigned short WAKE, unsigned short GAIN, unsigned short FREQ)
{
if ((VLEV < 16) && (FREQ < 4) && (GAIN < 4) && (WAKE < 2))
{
*pVR_CTL = ((WAKE << 8) | (VLEV << 4) | (GAIN << 2) | FREQ);
return 0;
}
else
return 1; //error, one or more of the values is out of range
}
//------------------------------------------------------------------------------//
// Function: Set_Op_Mode //
// //
// Parameters: Mode, MSEL //
// //
// Purpose: This function will automatically configure the PLL_DIV and PLL_CTL //
// registers for specific values of the core clock and system clock. //
// //
// Returns: Will return "true" if any parameter values are outside the //
// acceptable range. //
//------------------------------------------------------------------------------//
UCHAR Current_Mode;
UCHAR Set_Op_Mode(unsigned char New_Mode, unsigned int MSEL)
{
// Note: The global variable Current_Mode is used to determine which state the
// processor is currently in. This is important because certain operating mode
// transitions may cause unpredictable behavior.
// Full On = 1, Active = 2, Sleep = 3, Deep Sleep = 4
if (Current_Mode == 1)
{
if (New_Mode == 1)
{
//Do nothing, we are already in Full On mode
}
else if (New_Mode == 2) //Switch to Active mode: Bypass = 1, STOPCK = 0, PDWN = 0.
{
asm("CLI R2;"); /*disable interrupts, copy IMASK to R2 */
*pPLL_CTL = 0x7F00;
asm("IDLE;"); /*drain pipeline, enter idle state, wait for PLL wake-up */
asm("STI R2;"); /*after PLL wakeup occurs, restore interrupts and IMASK */
}
else if (New_Mode == 3) //Switch to Sleep mode: STOPCK = 1, PDWN = 0, PLL NOT bypassed.
{
asm("CLI R2;"); /*disable interrupts, copy IMASK to R2 */
*pPLL_CTL = 0x7E40;
asm("IDLE;"); /*drain pipeline, enter idle state, wait for PLL wake-up */
asm("STI R2;"); /*after PLL wakeup occurs, restore interrupts and IMASK */
}
else if (New_Mode == 4) //Switch to Deep Sleep mode:
{
asm("CLI R2;"); /*disable interrupts, copy IMASK to R2 */
*pPLL_CTL = 0x7F3A;
asm("IDLE;"); /*drain pipeline, enter idle state, wait for PLL wake-up */
asm("STI R2;"); /*after PLL wakeup occurs, restore interrupts and IMASK */
}
}
else if (Current_Mode == 2)
{
if (New_Mode == 1) //Switch to Full On mode: Bypass & PLL_OFF & STOPCK & PDWN = 0.
{
asm("CLI R2;"); /*disable interrupts, copy IMASK to R2 */
*pPLL_CTL = 0x7E00;
asm("IDLE;"); /*drain pipeline, enter idle state, wait for PLL wake-up */
asm("STI R2;"); /*after PLL wakeup occurs, restore interrupts and IMASK */
}
else if (New_Mode == 2)
{
// Do nothing, already in Active mode
}
else if (New_Mode == 3)
{
asm("CLI R2;"); /*disable interrupts, copy IMASK to R2 */
*pPLL_CTL = 0x7F40; //Switch to Sleep mode: STOPCK = 1, PDWN = 0, PLL bypassed.
asm("IDLE;"); /*drain pipeline, enter idle state, wait for PLL wake-up */
asm("STI R2;"); /*after PLL wakeup occurs, restore interrupts and IMASK */
}
else if (New_Mode == 4)
{
asm("CLI R2;"); /*disable interrupts, copy IMASK to R2 */
*pPLL_CTL = 0x7F3A;
asm("IDLE;"); /*drain pipeline, enter idle state, wait for PLL wake-up */
asm("STI R2;"); /*after PLL wakeup occurs, restore interrupts and IMASK */
}
}
else if (Current_Mode == 3)
{
if (New_Mode == 1) //Switch to Full On mode: Bypass & PLL_OFF & STOPCK & PDWN = 0.
{
asm("CLI R2;"); /*disable interrupts, copy IMASK to R2 */
*pPLL_CTL = 0x7E00;
asm("IDLE;"); /*drain pipeline, enter idle state, wait for PLL wake-up */
asm("STI R2;"); /*after PLL wakeup occurs, restore interrupts and IMASK */
}
else if (New_Mode == 2)
{
asm("CLI R2;"); /*disable interrupts, copy IMASK to R2 */
*pPLL_CTL = 0x7F00;
asm("IDLE;"); /*drain pipeline, enter idle state, wait for PLL wake-up */
asm("STI R2;"); /*after PLL wakeup occurs, restore interrupts and IMASK */
}
else if (New_Mode == 3)
{
//Do nothing, already in sleep mode
}
else if (New_Mode == 4)
{
return 0; //Error, transitioning from sleep to deep sleep may cause problems
}
}
else if (Current_Mode == 4)
{
if (New_Mode == 1) //Switch to Full On mode: Bypass & PLL_OFF & STOPCK & PDWN = 0.
{
asm("CLI R2;"); /*disable interrupts, copy IMASK to R2 */
*pPLL_CTL = 0x7E00;
asm("IDLE;"); /*drain pipeline, enter idle state, wait for PLL wake-up */
asm("STI R2;"); /*after PLL wakeup occurs, restore interrupts and IMASK */
}
else if (New_Mode == 2)
{
asm("CLI R2;"); /*disable interrupts, copy IMASK to R2 */
*pPLL_CTL = 0x7F00;
asm("IDLE;"); /*drain pipeline, enter idle state, wait for PLL wake-up */
asm("STI R2;"); /*after PLL wakeup occurs, restore interrupts and IMASK */
}
else if (New_Mode == 3)
{
//Do nothing, already in sleep mode
}
else if (New_Mode == 4)
{
return 0; //Error, transitioning from sleep to deep sleep may cause problems
}
}
return 1;
}
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