asci_traffic_light.v

用VERLOG实现交通灯程序

`define S0 2'b00 //main green country red
`define S1 2'b01 //main san country red
`define S2 2'b10 //main red country green'
`define S3 2'b11 //main red country san
module traffic(CLK,RESET,HG,HS,HR,FG,FS,FR,TIMEH,TIMEL);
input CLK,S,RESET;
output HG,HS,HR,FG,FS,FR;
reg HG,HS,HR,FG,FS,FR;
output [3:0] TIMEH;
output [3:0] TIMEL;
reg [3:0] TIMEH,TIMEL;
wire TM,TS,TF;
reg St;
reg [1:0] CurrentState,NextState;


always @(posedge CLK or negedge RESET)
	begin:counter
	if(~RESET) {TIMEH,TIMEL}=8'b0;
	else if(St) {TIMEH,TIMEL}=8'b0;
	//else if((TIMEH==9)&(TIMEL==9)) {TIMEH,TIMEL}=8'b0;
	else if(TIMEL==9)
		begin TIMEH=TIMEH+1;TIMEL=0;end
	else begin TIMEH=TIMEH;TIMEL=TIMEL+1;end
	end
	assign TS=(TIMEH==0)&(TIMEL==4);
	assign TM=(TIMEH==9)&(TIMEL==9);
	assign TF=(TIMEH==2)&(TIMEL==9);



always@(posedge CLK or negedge RESET)
	begin:statereg
	if(~RESET)
		CurrrentState<='S0;
	else CurrentState<=NextState;
	end

always@(CurrentState or TS or TM or TF)
	begin:fsm
		case(CurrentState)
			S0:begin
				NextState = TM?'S1:'S0;
				St=TM?1:0;
				end
			S1:begin
				NextState=TS?'S2:'S1;
				St=TY?1:0;
				end
			S2:begin
				NextState=TF?'S3:'S2;
				St=TF?1:0;
				end
			S3:begin
				NextState=TS?'S0:'S3;
				St=TS?1:0;
				end
		endcase
    end





always@(CurrentState)
	begin
		case(CurrentState)
			'S0:begin
				{HG,HS,HR}=3'b100;
				{FG,FS,FR}=3'b001;
				end
			'S1:begin
				if(TS[0]||TS[2]||TS[4])
					{HG,HS,HR}=3'b010;
				else {HG,HS,HR}=3'b000;
				{FG,FS,FR}=3'b001;
				end
			'S2:begin
				{HG,HS,HR}=3'b001;
				{FG,FS,FR}=3'b100;
				end
            'S3:begin
				if(TS[0]||TS[2]||TS[4])
					{HG,HS,HR}=3'b010;
				else {HG,HS,HR}=3'b000;
				{FG,FS,FR}=3'b100;
				end
		endcase
end
endmodule