mult_m5q.tdf

该源码实现了一个8*8位的乘法器

--lpm_mult CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Stratix" DSP_BLOCK_BALANCING="Auto" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTHA=8 LPM_WIDTHB=8 LPM_WIDTHP=16 LPM_WIDTHS=1 MAXIMIZE_SPEED=5 clock dataa datab result CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=70
--VERSION_BEGIN 4.2 cbx_cycloneii 2004:08:25:19:39:42:SJ cbx_lpm_add_sub 2004:10:25:10:56:48:SJ cbx_lpm_mult 2004:10:14:16:46:16:SJ cbx_mgl 2004:12:23:09:14:54:SJ cbx_padd 2004:10:28:17:00:18:SJ cbx_stratix 2004:09:23:18:28:34:SJ cbx_stratixii 2004:08:10:15:01:36:SJ cbx_util_mgl 2004:09:29:16:04:00:SJ  VERSION_END


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FUNCTION stratix_mac_mult (aclr[3..0], clk[3..0], dataa[17..0], datab[17..0], ena[3..0], signa, signb)
WITH ( 	dataa_clear,	dataa_clock,	dataa_width,	datab_clear,	datab_clock,	datab_width,	output_clear,	output_clock,	signa_clear,	signa_clock,	signa_internally_grounded,	signb_clear,	signb_clock,	signb_internally_grounded) 
RETURNS ( dataout[35..0], scanouta[17..0], scanoutb[17..0]);
PARAMETERS
(
	dataout_width = 72
);
FUNCTION stratix_mac_out (aclr[3..0], addnsub0, addnsub1, clk[3..0], dataa[35..0], datab[35..0], datac[35..0], datad[35..0], ena[3..0], signa, signb, zeroacc)
WITH ( 	addnsub0_clear,	addnsub0_clock,	addnsub0_pipeline_clear,	addnsub0_pipeline_clock,	addnsub1_clear,	addnsub1_clock,	addnsub1_pipeline_clear,	addnsub1_pipeline_clock,	dataa_width,	datab_width,	datac_width,	datad_width,	dataout_width,	operation_mode,	output_clear,	output_clock,	signa_clear,	signa_clock,	signa_pipeline_clear,	signa_pipeline_clock,	signb_clear,	signb_clock,	signb_pipeline_clear,	signb_pipeline_clock,	zeroacc_clear,	zeroacc_clock,	zeroacc_pipeline_clear,	zeroacc_pipeline_clock) 
RETURNS ( accoverflow, dataout[dataout_width-1..0]);

--synthesis_resources = dsp_9bit 1 
SUBDESIGN mult_m5q
( 
	clock	:	input;
	dataa[7..0]	:	input;
	datab[7..0]	:	input;
	result[15..0]	:	output;
) 
VARIABLE 
	mac_mult2 : stratix_mac_mult
		WITH (
			dataa_clear = "0",
			dataa_clock = "0",
			dataa_width = 8,
			datab_clear = "0",
			datab_clock = "0",
			datab_width = 8
		);
	mac_out1 : stratix_mac_out
		WITH (
			dataa_width = 16,
			dataout_width = 72,
			operation_mode = "output_only"
		);
	aclr	: NODE;
	clken	: NODE;

BEGIN 
	mac_mult2.aclr[] = aclr;
	mac_mult2.clk[] = clock;
	mac_mult2.dataa[] = ( B"1111111111", dataa[]);
	mac_mult2.datab[] = ( B"1111111111", datab[]);
	mac_mult2.ena[] = clken;
	mac_mult2.signa = B"0";
	mac_mult2.signb = B"0";
	mac_out1.aclr[] = aclr;
	mac_out1.clk[] = clock;
	mac_out1.dataa[] = ( B"00000000000000000000", mac_mult2.dataout[15..0]);
	mac_out1.ena[] = clken;
	mac_out1.signa = B"0";
	mac_out1.signb = B"0";
	aclr = GND;
	clken = VCC;
	result[15..0] = mac_out1.dataout[15..0];
END;
--VALID FILE