pipemult.hier_info

该源码实现了一个8*8位的乘法器

address_b[0] => ram_block1a0.PORTBADDR
address_b[0] => ram_block1a1.PORTBADDR
address_b[0] => ram_block1a2.PORTBADDR
address_b[0] => ram_block1a3.PORTBADDR
address_b[0] => ram_block1a4.PORTBADDR
address_b[0] => ram_block1a5.PORTBADDR
address_b[0] => ram_block1a6.PORTBADDR
address_b[0] => ram_block1a7.PORTBADDR
address_b[0] => ram_block1a8.PORTBADDR
address_b[0] => ram_block1a9.PORTBADDR
address_b[0] => ram_block1a10.PORTBADDR
address_b[0] => ram_block1a11.PORTBADDR
address_b[0] => ram_block1a12.PORTBADDR
address_b[0] => ram_block1a13.PORTBADDR
address_b[0] => ram_block1a14.PORTBADDR
address_b[0] => ram_block1a15.PORTBADDR
address_b[1] => ram_block1a0.PORTBADDR1
address_b[1] => ram_block1a1.PORTBADDR1
address_b[1] => ram_block1a2.PORTBADDR1
address_b[1] => ram_block1a3.PORTBADDR1
address_b[1] => ram_block1a4.PORTBADDR1
address_b[1] => ram_block1a5.PORTBADDR1
address_b[1] => ram_block1a6.PORTBADDR1
address_b[1] => ram_block1a7.PORTBADDR1
address_b[1] => ram_block1a8.PORTBADDR1
address_b[1] => ram_block1a9.PORTBADDR1
address_b[1] => ram_block1a10.PORTBADDR1
address_b[1] => ram_block1a11.PORTBADDR1
address_b[1] => ram_block1a12.PORTBADDR1
address_b[1] => ram_block1a13.PORTBADDR1
address_b[1] => ram_block1a14.PORTBADDR1
address_b[1] => ram_block1a15.PORTBADDR1
address_b[2] => ram_block1a0.PORTBADDR2
address_b[2] => ram_block1a1.PORTBADDR2
address_b[2] => ram_block1a2.PORTBADDR2
address_b[2] => ram_block1a3.PORTBADDR2
address_b[2] => ram_block1a4.PORTBADDR2
address_b[2] => ram_block1a5.PORTBADDR2
address_b[2] => ram_block1a6.PORTBADDR2
address_b[2] => ram_block1a7.PORTBADDR2
address_b[2] => ram_block1a8.PORTBADDR2
address_b[2] => ram_block1a9.PORTBADDR2
address_b[2] => ram_block1a10.PORTBADDR2
address_b[2] => ram_block1a11.PORTBADDR2
address_b[2] => ram_block1a12.PORTBADDR2
address_b[2] => ram_block1a13.PORTBADDR2
address_b[2] => ram_block1a14.PORTBADDR2
address_b[2] => ram_block1a15.PORTBADDR2
address_b[3] => ram_block1a0.PORTBADDR3
address_b[3] => ram_block1a1.PORTBADDR3
address_b[3] => ram_block1a2.PORTBADDR3
address_b[3] => ram_block1a3.PORTBADDR3
address_b[3] => ram_block1a4.PORTBADDR3
address_b[3] => ram_block1a5.PORTBADDR3
address_b[3] => ram_block1a6.PORTBADDR3
address_b[3] => ram_block1a7.PORTBADDR3
address_b[3] => ram_block1a8.PORTBADDR3
address_b[3] => ram_block1a9.PORTBADDR3
address_b[3] => ram_block1a10.PORTBADDR3
address_b[3] => ram_block1a11.PORTBADDR3
address_b[3] => ram_block1a12.PORTBADDR3
address_b[3] => ram_block1a13.PORTBADDR3
address_b[3] => ram_block1a14.PORTBADDR3
address_b[3] => ram_block1a15.PORTBADDR3
address_b[4] => ram_block1a0.PORTBADDR4
address_b[4] => ram_block1a1.PORTBADDR4
address_b[4] => ram_block1a2.PORTBADDR4
address_b[4] => ram_block1a3.PORTBADDR4
address_b[4] => ram_block1a4.PORTBADDR4
address_b[4] => ram_block1a5.PORTBADDR4
address_b[4] => ram_block1a6.PORTBADDR4
address_b[4] => ram_block1a7.PORTBADDR4
address_b[4] => ram_block1a8.PORTBADDR4
address_b[4] => ram_block1a9.PORTBADDR4
address_b[4] => ram_block1a10.PORTBADDR4
address_b[4] => ram_block1a11.PORTBADDR4
address_b[4] => ram_block1a12.PORTBADDR4
address_b[4] => ram_block1a13.PORTBADDR4
address_b[4] => ram_block1a14.PORTBADDR4
address_b[4] => ram_block1a15.PORTBADDR4
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock0 => ram_block1a8.CLK0
clock0 => ram_block1a9.CLK0
clock0 => ram_block1a10.CLK0
clock0 => ram_block1a11.CLK0
clock0 => ram_block1a12.CLK0
clock0 => ram_block1a13.CLK0
clock0 => ram_block1a14.CLK0
clock0 => ram_block1a15.CLK0
data_a[0] => ram_block1a0.PORTADATAIN
data_a[1] => ram_block1a1.PORTADATAIN
data_a[2] => ram_block1a2.PORTADATAIN
data_a[3] => ram_block1a3.PORTADATAIN
data_a[4] => ram_block1a4.PORTADATAIN
data_a[5] => ram_block1a5.PORTADATAIN
data_a[6] => ram_block1a6.PORTADATAIN
data_a[7] => ram_block1a7.PORTADATAIN
data_a[8] => ram_block1a8.PORTADATAIN
data_a[9] => ram_block1a9.PORTADATAIN
data_a[10] => ram_block1a10.PORTADATAIN
data_a[11] => ram_block1a11.PORTADATAIN
data_a[12] => ram_block1a12.PORTADATAIN
data_a[13] => ram_block1a13.PORTADATAIN
data_a[14] => ram_block1a14.PORTADATAIN
data_a[15] => ram_block1a15.PORTADATAIN
q_b[0] <= ram_block1a0.PORTBDATAOUT
q_b[1] <= ram_block1a1.PORTBDATAOUT
q_b[2] <= ram_block1a2.PORTBDATAOUT
q_b[3] <= ram_block1a3.PORTBDATAOUT
q_b[4] <= ram_block1a4.PORTBDATAOUT
q_b[5] <= ram_block1a5.PORTBDATAOUT
q_b[6] <= ram_block1a6.PORTBDATAOUT
q_b[7] <= ram_block1a7.PORTBDATAOUT
q_b[8] <= ram_block1a8.PORTBDATAOUT
q_b[9] <= ram_block1a9.PORTBDATAOUT
q_b[10] <= ram_block1a10.PORTBDATAOUT
q_b[11] <= ram_block1a11.PORTBDATAOUT
q_b[12] <= ram_block1a12.PORTBDATAOUT
q_b[13] <= ram_block1a13.PORTBDATAOUT
q_b[14] <= ram_block1a14.PORTBDATAOUT
q_b[15] <= ram_block1a15.PORTBDATAOUT
wren_a => ram_block1a0.PORTAWE
wren_a => ram_block1a1.PORTAWE
wren_a => ram_block1a2.PORTAWE
wren_a => ram_block1a3.PORTAWE
wren_a => ram_block1a4.PORTAWE
wren_a => ram_block1a5.PORTAWE
wren_a => ram_block1a6.PORTAWE
wren_a => ram_block1a7.PORTAWE
wren_a => ram_block1a8.PORTAWE
wren_a => ram_block1a9.PORTAWE
wren_a => ram_block1a10.PORTAWE
wren_a => ram_block1a11.PORTAWE
wren_a => ram_block1a12.PORTAWE
wren_a => ram_block1a13.PORTAWE
wren_a => ram_block1a14.PORTAWE
wren_a => ram_block1a15.PORTAWE


|pipemult|mult:inst
dataa[0] => dataa[0]~7.IN1
dataa[1] => dataa[1]~6.IN1
dataa[2] => dataa[2]~5.IN1
dataa[3] => dataa[3]~4.IN1
dataa[4] => dataa[4]~3.IN1
dataa[5] => dataa[5]~2.IN1
dataa[6] => dataa[6]~1.IN1
dataa[7] => dataa[7]~0.IN1
datab[0] => datab[0]~7.IN1
datab[1] => datab[1]~6.IN1
datab[2] => datab[2]~5.IN1
datab[3] => datab[3]~4.IN1
datab[4] => datab[4]~3.IN1
datab[5] => datab[5]~2.IN1
datab[6] => datab[6]~1.IN1
datab[7] => datab[7]~0.IN1
clock => clock~0.IN1
result[0] <= lpm_mult:lpm_mult_component.result
result[1] <= lpm_mult:lpm_mult_component.result
result[2] <= lpm_mult:lpm_mult_component.result
result[3] <= lpm_mult:lpm_mult_component.result
result[4] <= lpm_mult:lpm_mult_component.result
result[5] <= lpm_mult:lpm_mult_component.result
result[6] <= lpm_mult:lpm_mult_component.result
result[7] <= lpm_mult:lpm_mult_component.result
result[8] <= lpm_mult:lpm_mult_component.result
result[9] <= lpm_mult:lpm_mult_component.result
result[10] <= lpm_mult:lpm_mult_component.result
result[11] <= lpm_mult:lpm_mult_component.result
result[12] <= lpm_mult:lpm_mult_component.result
result[13] <= lpm_mult:lpm_mult_component.result
result[14] <= lpm_mult:lpm_mult_component.result
result[15] <= lpm_mult:lpm_mult_component.result


|pipemult|mult:inst|lpm_mult:lpm_mult_component
dataa[0] => mult_m5q:auto_generated.dataa[0]
dataa[1] => mult_m5q:auto_generated.dataa[1]
dataa[2] => mult_m5q:auto_generated.dataa[2]
dataa[3] => mult_m5q:auto_generated.dataa[3]
dataa[4] => mult_m5q:auto_generated.dataa[4]
dataa[5] => mult_m5q:auto_generated.dataa[5]
dataa[6] => mult_m5q:auto_generated.dataa[6]
dataa[7] => mult_m5q:auto_generated.dataa[7]
datab[0] => mult_m5q:auto_generated.datab[0]
datab[1] => mult_m5q:auto_generated.datab[1]
datab[2] => mult_m5q:auto_generated.datab[2]
datab[3] => mult_m5q:auto_generated.datab[3]
datab[4] => mult_m5q:auto_generated.datab[4]
datab[5] => mult_m5q:auto_generated.datab[5]
datab[6] => mult_m5q:auto_generated.datab[6]
datab[7] => mult_m5q:auto_generated.datab[7]
sum[0] => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clock => mult_m5q:auto_generated.clock
clken => ~NO_FANOUT~
result[0] <= mult_m5q:auto_generated.result[0]
result[1] <= mult_m5q:auto_generated.result[1]
result[2] <= mult_m5q:auto_generated.result[2]
result[3] <= mult_m5q:auto_generated.result[3]
result[4] <= mult_m5q:auto_generated.result[4]
result[5] <= mult_m5q:auto_generated.result[5]
result[6] <= mult_m5q:auto_generated.result[6]
result[7] <= mult_m5q:auto_generated.result[7]
result[8] <= mult_m5q:auto_generated.result[8]
result[9] <= mult_m5q:auto_generated.result[9]
result[10] <= mult_m5q:auto_generated.result[10]
result[11] <= mult_m5q:auto_generated.result[11]
result[12] <= mult_m5q:auto_generated.result[12]
result[13] <= mult_m5q:auto_generated.result[13]
result[14] <= mult_m5q:auto_generated.result[14]
result[15] <= mult_m5q:auto_generated.result[15]


|pipemult|mult:inst|lpm_mult:lpm_mult_component|mult_m5q:auto_generated
clock => mac_mult2.CLK
clock => mac_mult2.CLK1
clock => mac_mult2.CLK2
clock => mac_mult2.CLK3
clock => mac_out1.CLK
clock => mac_out1.CLK1
clock => mac_out1.CLK2
clock => mac_out1.CLK3
dataa[0] => mac_mult2.DATAA
dataa[1] => mac_mult2.DATAA1
dataa[2] => mac_mult2.DATAA2
dataa[3] => mac_mult2.DATAA3
dataa[4] => mac_mult2.DATAA4
dataa[5] => mac_mult2.DATAA5
dataa[6] => mac_mult2.DATAA6
dataa[7] => mac_mult2.DATAA7
datab[0] => mac_mult2.DATAB
datab[1] => mac_mult2.DATAB1
datab[2] => mac_mult2.DATAB2
datab[3] => mac_mult2.DATAB3
datab[4] => mac_mult2.DATAB4
datab[5] => mac_mult2.DATAB5
datab[6] => mac_mult2.DATAB6
datab[7] => mac_mult2.DATAB7
result[0] <= mac_out1.DATAOUT
result[1] <= mac_out1.DATAOUT1
result[2] <= mac_out1.DATAOUT2
result[3] <= mac_out1.DATAOUT3
result[4] <= mac_out1.DATAOUT4
result[5] <= mac_out1.DATAOUT5
result[6] <= mac_out1.DATAOUT6
result[7] <= mac_out1.DATAOUT7
result[8] <= mac_out1.DATAOUT8
result[9] <= mac_out1.DATAOUT9
result[10] <= mac_out1.DATAOUT10
result[11] <= mac_out1.DATAOUT11
result[12] <= mac_out1.DATAOUT12
result[13] <= mac_out1.DATAOUT13
result[14] <= mac_out1.DATAOUT14
result[15] <= mac_out1.DATAOUT15