pipemult.hier_info

该源码实现了一个8*8位的乘法器

|pipemult
q[0] <= lpm_ram_dp0:inst1.q[0]
q[1] <= lpm_ram_dp0:inst1.q[1]
q[2] <= lpm_ram_dp0:inst1.q[2]
q[3] <= lpm_ram_dp0:inst1.q[3]
q[4] <= lpm_ram_dp0:inst1.q[4]
q[5] <= lpm_ram_dp0:inst1.q[5]
q[6] <= lpm_ram_dp0:inst1.q[6]
q[7] <= lpm_ram_dp0:inst1.q[7]
q[8] <= lpm_ram_dp0:inst1.q[8]
q[9] <= lpm_ram_dp0:inst1.q[9]
q[10] <= lpm_ram_dp0:inst1.q[10]
q[11] <= lpm_ram_dp0:inst1.q[11]
q[12] <= lpm_ram_dp0:inst1.q[12]
q[13] <= lpm_ram_dp0:inst1.q[13]
q[14] <= lpm_ram_dp0:inst1.q[14]
q[15] <= lpm_ram_dp0:inst1.q[15]
wren => lpm_ram_dp0:inst1.wren
clk1 => lpm_ram_dp0:inst1.clock
clk1 => mult:inst.clock
dataa[0] => mult:inst.dataa[0]
dataa[1] => mult:inst.dataa[1]
dataa[2] => mult:inst.dataa[2]
dataa[3] => mult:inst.dataa[3]
dataa[4] => mult:inst.dataa[4]
dataa[5] => mult:inst.dataa[5]
dataa[6] => mult:inst.dataa[6]
dataa[7] => mult:inst.dataa[7]
datab[0] => mult:inst.datab[0]
datab[1] => mult:inst.datab[1]
datab[2] => mult:inst.datab[2]
datab[3] => mult:inst.datab[3]
datab[4] => mult:inst.datab[4]
datab[5] => mult:inst.datab[5]
datab[6] => mult:inst.datab[6]
datab[7] => mult:inst.datab[7]
rdaddress[0] => lpm_ram_dp0:inst1.rdaddress[0]
rdaddress[1] => lpm_ram_dp0:inst1.rdaddress[1]
rdaddress[2] => lpm_ram_dp0:inst1.rdaddress[2]
rdaddress[3] => lpm_ram_dp0:inst1.rdaddress[3]
rdaddress[4] => lpm_ram_dp0:inst1.rdaddress[4]
wraddress[0] => lpm_ram_dp0:inst1.wraddress[0]
wraddress[1] => lpm_ram_dp0:inst1.wraddress[1]
wraddress[2] => lpm_ram_dp0:inst1.wraddress[2]
wraddress[3] => lpm_ram_dp0:inst1.wraddress[3]
wraddress[4] => lpm_ram_dp0:inst1.wraddress[4]


|pipemult|lpm_ram_dp0:inst1
data[0] => data[0]~15.IN1
data[1] => data[1]~14.IN1
data[2] => data[2]~13.IN1
data[3] => data[3]~12.IN1
data[4] => data[4]~11.IN1
data[5] => data[5]~10.IN1
data[6] => data[6]~9.IN1
data[7] => data[7]~8.IN1
data[8] => data[8]~7.IN1
data[9] => data[9]~6.IN1
data[10] => data[10]~5.IN1
data[11] => data[11]~4.IN1
data[12] => data[12]~3.IN1
data[13] => data[13]~2.IN1
data[14] => data[14]~1.IN1
data[15] => data[15]~0.IN1
wren => wren~0.IN1
wraddress[0] => wraddress[0]~4.IN1
wraddress[1] => wraddress[1]~3.IN1
wraddress[2] => wraddress[2]~2.IN1
wraddress[3] => wraddress[3]~1.IN1
wraddress[4] => wraddress[4]~0.IN1
rdaddress[0] => rdaddress[0]~4.IN1
rdaddress[1] => rdaddress[1]~3.IN1
rdaddress[2] => rdaddress[2]~2.IN1
rdaddress[3] => rdaddress[3]~1.IN1
rdaddress[4] => rdaddress[4]~0.IN1
clock => clock~0.IN1
q[0] <= altsyncram:altsyncram_component.q_b
q[1] <= altsyncram:altsyncram_component.q_b
q[2] <= altsyncram:altsyncram_component.q_b
q[3] <= altsyncram:altsyncram_component.q_b
q[4] <= altsyncram:altsyncram_component.q_b
q[5] <= altsyncram:altsyncram_component.q_b
q[6] <= altsyncram:altsyncram_component.q_b
q[7] <= altsyncram:altsyncram_component.q_b
q[8] <= altsyncram:altsyncram_component.q_b
q[9] <= altsyncram:altsyncram_component.q_b
q[10] <= altsyncram:altsyncram_component.q_b
q[11] <= altsyncram:altsyncram_component.q_b
q[12] <= altsyncram:altsyncram_component.q_b
q[13] <= altsyncram:altsyncram_component.q_b
q[14] <= altsyncram:altsyncram_component.q_b
q[15] <= altsyncram:altsyncram_component.q_b


|pipemult|lpm_ram_dp0:inst1|altsyncram:altsyncram_component
wren_a => altsyncram_g691:auto_generated.wren_a
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => altsyncram_g691:auto_generated.data_a[0]
data_a[1] => altsyncram_g691:auto_generated.data_a[1]
data_a[2] => altsyncram_g691:auto_generated.data_a[2]
data_a[3] => altsyncram_g691:auto_generated.data_a[3]
data_a[4] => altsyncram_g691:auto_generated.data_a[4]
data_a[5] => altsyncram_g691:auto_generated.data_a[5]
data_a[6] => altsyncram_g691:auto_generated.data_a[6]
data_a[7] => altsyncram_g691:auto_generated.data_a[7]
data_a[8] => altsyncram_g691:auto_generated.data_a[8]
data_a[9] => altsyncram_g691:auto_generated.data_a[9]
data_a[10] => altsyncram_g691:auto_generated.data_a[10]
data_a[11] => altsyncram_g691:auto_generated.data_a[11]
data_a[12] => altsyncram_g691:auto_generated.data_a[12]
data_a[13] => altsyncram_g691:auto_generated.data_a[13]
data_a[14] => altsyncram_g691:auto_generated.data_a[14]
data_a[15] => altsyncram_g691:auto_generated.data_a[15]
data_b[0] => ~NO_FANOUT~
data_b[1] => ~NO_FANOUT~
data_b[2] => ~NO_FANOUT~
data_b[3] => ~NO_FANOUT~
data_b[4] => ~NO_FANOUT~
data_b[5] => ~NO_FANOUT~
data_b[6] => ~NO_FANOUT~
data_b[7] => ~NO_FANOUT~
data_b[8] => ~NO_FANOUT~
data_b[9] => ~NO_FANOUT~
data_b[10] => ~NO_FANOUT~
data_b[11] => ~NO_FANOUT~
data_b[12] => ~NO_FANOUT~
data_b[13] => ~NO_FANOUT~
data_b[14] => ~NO_FANOUT~
data_b[15] => ~NO_FANOUT~
address_a[0] => altsyncram_g691:auto_generated.address_a[0]
address_a[1] => altsyncram_g691:auto_generated.address_a[1]
address_a[2] => altsyncram_g691:auto_generated.address_a[2]
address_a[3] => altsyncram_g691:auto_generated.address_a[3]
address_a[4] => altsyncram_g691:auto_generated.address_a[4]
address_b[0] => altsyncram_g691:auto_generated.address_b[0]
address_b[1] => altsyncram_g691:auto_generated.address_b[1]
address_b[2] => altsyncram_g691:auto_generated.address_b[2]
address_b[3] => altsyncram_g691:auto_generated.address_b[3]
address_b[4] => altsyncram_g691:auto_generated.address_b[4]
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_g691:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= <UNC>
q_a[1] <= <UNC>
q_a[2] <= <UNC>
q_a[3] <= <UNC>
q_a[4] <= <UNC>
q_a[5] <= <UNC>
q_a[6] <= <UNC>
q_a[7] <= <UNC>
q_a[8] <= <UNC>
q_a[9] <= <UNC>
q_a[10] <= <UNC>
q_a[11] <= <UNC>
q_a[12] <= <UNC>
q_a[13] <= <UNC>
q_a[14] <= <UNC>
q_a[15] <= <UNC>
q_b[0] <= altsyncram_g691:auto_generated.q_b[0]
q_b[1] <= altsyncram_g691:auto_generated.q_b[1]
q_b[2] <= altsyncram_g691:auto_generated.q_b[2]
q_b[3] <= altsyncram_g691:auto_generated.q_b[3]
q_b[4] <= altsyncram_g691:auto_generated.q_b[4]
q_b[5] <= altsyncram_g691:auto_generated.q_b[5]
q_b[6] <= altsyncram_g691:auto_generated.q_b[6]
q_b[7] <= altsyncram_g691:auto_generated.q_b[7]
q_b[8] <= altsyncram_g691:auto_generated.q_b[8]
q_b[9] <= altsyncram_g691:auto_generated.q_b[9]
q_b[10] <= altsyncram_g691:auto_generated.q_b[10]
q_b[11] <= altsyncram_g691:auto_generated.q_b[11]
q_b[12] <= altsyncram_g691:auto_generated.q_b[12]
q_b[13] <= altsyncram_g691:auto_generated.q_b[13]
q_b[14] <= altsyncram_g691:auto_generated.q_b[14]
q_b[15] <= altsyncram_g691:auto_generated.q_b[15]


|pipemult|lpm_ram_dp0:inst1|altsyncram:altsyncram_component|altsyncram_g691:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[0] => ram_block1a10.PORTAADDR
address_a[0] => ram_block1a11.PORTAADDR
address_a[0] => ram_block1a12.PORTAADDR
address_a[0] => ram_block1a13.PORTAADDR
address_a[0] => ram_block1a14.PORTAADDR
address_a[0] => ram_block1a15.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[1] => ram_block1a8.PORTAADDR1
address_a[1] => ram_block1a9.PORTAADDR1
address_a[1] => ram_block1a10.PORTAADDR1
address_a[1] => ram_block1a11.PORTAADDR1
address_a[1] => ram_block1a12.PORTAADDR1
address_a[1] => ram_block1a13.PORTAADDR1
address_a[1] => ram_block1a14.PORTAADDR1
address_a[1] => ram_block1a15.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[2] => ram_block1a8.PORTAADDR2
address_a[2] => ram_block1a9.PORTAADDR2
address_a[2] => ram_block1a10.PORTAADDR2
address_a[2] => ram_block1a11.PORTAADDR2
address_a[2] => ram_block1a12.PORTAADDR2
address_a[2] => ram_block1a13.PORTAADDR2
address_a[2] => ram_block1a14.PORTAADDR2
address_a[2] => ram_block1a15.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[3] => ram_block1a8.PORTAADDR3
address_a[3] => ram_block1a9.PORTAADDR3
address_a[3] => ram_block1a10.PORTAADDR3
address_a[3] => ram_block1a11.PORTAADDR3
address_a[3] => ram_block1a12.PORTAADDR3
address_a[3] => ram_block1a13.PORTAADDR3
address_a[3] => ram_block1a14.PORTAADDR3
address_a[3] => ram_block1a15.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[4] => ram_block1a8.PORTAADDR4
address_a[4] => ram_block1a9.PORTAADDR4
address_a[4] => ram_block1a10.PORTAADDR4
address_a[4] => ram_block1a11.PORTAADDR4
address_a[4] => ram_block1a12.PORTAADDR4
address_a[4] => ram_block1a13.PORTAADDR4
address_a[4] => ram_block1a14.PORTAADDR4
address_a[4] => ram_block1a15.PORTAADDR4