pipemult.map.eqn

该源码实现了一个8*8位的乘法器

--G1_q_b[15] is lpm_ram_dp0:inst1|altsyncram:altsyncram_component|altsyncram_g691:auto_generated|q_b[15]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
G1_q_b[15]_PORT_A_data_in = E1_result[15];
G1_q_b[15]_PORT_A_data_in_reg = DFFE(G1_q_b[15]_PORT_A_data_in, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[15]_PORT_A_address_reg = DFFE(G1_q_b[15]_PORT_A_address, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_B_address = BUS(rdaddress[0], rdaddress[1], rdaddress[2], rdaddress[3], rdaddress[4]);
G1_q_b[15]_PORT_B_address_reg = DFFE(G1_q_b[15]_PORT_B_address, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_A_write_enable = wren;
G1_q_b[15]_PORT_A_write_enable_reg = DFFE(G1_q_b[15]_PORT_A_write_enable, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_B_read_enable = VCC;
G1_q_b[15]_PORT_B_read_enable_reg = DFFE(G1_q_b[15]_PORT_B_read_enable, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_clock_0 = clk1;
G1_q_b[15]_PORT_B_data_out = MEMORY(G1_q_b[15]_PORT_A_data_in_reg, , G1_q_b[15]_PORT_A_address_reg, G1_q_b[15]_PORT_B_address_reg, G1_q_b[15]_PORT_A_write_enable_reg, G1_q_b[15]_PORT_B_read_enable_reg, , , G1_q_b[15]_clock_0, , , , , );
G1_q_b[15] = G1_q_b[15]_PORT_B_data_out[0];


--G1_q_b[14] is lpm_ram_dp0:inst1|altsyncram:altsyncram_component|altsyncram_g691:auto_generated|q_b[14]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
G1_q_b[14]_PORT_A_data_in = E1_result[14];
G1_q_b[14]_PORT_A_data_in_reg = DFFE(G1_q_b[14]_PORT_A_data_in, G1_q_b[14]_clock_0, , , );
G1_q_b[14]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[14]_PORT_A_address_reg = DFFE(G1_q_b[14]_PORT_A_address, G1_q_b[14]_clock_0, , , );
G1_q_b[14]_PORT_B_address = BUS(rdaddress[0], rdaddress[1], rdaddress[2], rdaddress[3], rdaddress[4]);
G1_q_b[14]_PORT_B_address_reg = DFFE(G1_q_b[14]_PORT_B_address, G1_q_b[14]_clock_0, , , );
G1_q_b[14]_PORT_A_write_enable = wren;
G1_q_b[14]_PORT_A_write_enable_reg = DFFE(G1_q_b[14]_PORT_A_write_enable, G1_q_b[14]_clock_0, , , );
G1_q_b[14]_PORT_B_read_enable = VCC;
G1_q_b[14]_PORT_B_read_enable_reg = DFFE(G1_q_b[14]_PORT_B_read_enable, G1_q_b[14]_clock_0, , , );
G1_q_b[14]_clock_0 = clk1;
G1_q_b[14]_PORT_B_data_out = MEMORY(G1_q_b[14]_PORT_A_data_in_reg, , G1_q_b[14]_PORT_A_address_reg, G1_q_b[14]_PORT_B_address_reg, G1_q_b[14]_PORT_A_write_enable_reg, G1_q_b[14]_PORT_B_read_enable_reg, , , G1_q_b[14]_clock_0, , , , , );
G1_q_b[14] = G1_q_b[14]_PORT_B_data_out[0];


--G1_q_b[13] is lpm_ram_dp0:inst1|altsyncram:altsyncram_component|altsyncram_g691:auto_generated|q_b[13]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
G1_q_b[13]_PORT_A_data_in = E1_result[13];
G1_q_b[13]_PORT_A_data_in_reg = DFFE(G1_q_b[13]_PORT_A_data_in, G1_q_b[13]_clock_0, , , );
G1_q_b[13]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[13]_PORT_A_address_reg = DFFE(G1_q_b[13]_PORT_A_address, G1_q_b[13]_clock_0, , , );
G1_q_b[13]_PORT_B_address = BUS(rdaddress[0], rdaddress[1], rdaddress[2], rdaddress[3], rdaddress[4]);
G1_q_b[13]_PORT_B_address_reg = DFFE(G1_q_b[13]_PORT_B_address, G1_q_b[13]_clock_0, , , );
G1_q_b[13]_PORT_A_write_enable = wren;
G1_q_b[13]_PORT_A_write_enable_reg = DFFE(G1_q_b[13]_PORT_A_write_enable, G1_q_b[13]_clock_0, , , );
G1_q_b[13]_PORT_B_read_enable = VCC;
G1_q_b[13]_PORT_B_read_enable_reg = DFFE(G1_q_b[13]_PORT_B_read_enable, G1_q_b[13]_clock_0, , , );
G1_q_b[13]_clock_0 = clk1;
G1_q_b[13]_PORT_B_data_out = MEMORY(G1_q_b[13]_PORT_A_data_in_reg, , G1_q_b[13]_PORT_A_address_reg, G1_q_b[13]_PORT_B_address_reg, G1_q_b[13]_PORT_A_write_enable_reg, G1_q_b[13]_PORT_B_read_enable_reg, , , G1_q_b[13]_clock_0, , , , , );
G1_q_b[13] = G1_q_b[13]_PORT_B_data_out[0];


--G1_q_b[12] is lpm_ram_dp0:inst1|altsyncram:altsyncram_component|altsyncram_g691:auto_generated|q_b[12]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
G1_q_b[12]_PORT_A_data_in = E1_result[12];
G1_q_b[12]_PORT_A_data_in_reg = DFFE(G1_q_b[12]_PORT_A_data_in, G1_q_b[12]_clock_0, , , );
G1_q_b[12]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[12]_PORT_A_address_reg = DFFE(G1_q_b[12]_PORT_A_address, G1_q_b[12]_clock_0, , , );
G1_q_b[12]_PORT_B_address = BUS(rdaddress[0], rdaddress[1], rdaddress[2], rdaddress[3], rdaddress[4]);
G1_q_b[12]_PORT_B_address_reg = DFFE(G1_q_b[12]_PORT_B_address, G1_q_b[12]_clock_0, , , );
G1_q_b[12]_PORT_A_write_enable = wren;
G1_q_b[12]_PORT_A_write_enable_reg = DFFE(G1_q_b[12]_PORT_A_write_enable, G1_q_b[12]_clock_0, , , );
G1_q_b[12]_PORT_B_read_enable = VCC;
G1_q_b[12]_PORT_B_read_enable_reg = DFFE(G1_q_b[12]_PORT_B_read_enable, G1_q_b[12]_clock_0, , , );
G1_q_b[12]_clock_0 = clk1;
G1_q_b[12]_PORT_B_data_out = MEMORY(G1_q_b[12]_PORT_A_data_in_reg, , G1_q_b[12]_PORT_A_address_reg, G1_q_b[12]_PORT_B_address_reg, G1_q_b[12]_PORT_A_write_enable_reg, G1_q_b[12]_PORT_B_read_enable_reg, , , G1_q_b[12]_clock_0, , , , , );
G1_q_b[12] = G1_q_b[12]_PORT_B_data_out[0];


--G1_q_b[11] is lpm_ram_dp0:inst1|altsyncram:altsyncram_component|altsyncram_g691:auto_generated|q_b[11]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
G1_q_b[11]_PORT_A_data_in = E1_result[11];
G1_q_b[11]_PORT_A_data_in_reg = DFFE(G1_q_b[11]_PORT_A_data_in, G1_q_b[11]_clock_0, , , );
G1_q_b[11]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[11]_PORT_A_address_reg = DFFE(G1_q_b[11]_PORT_A_address, G1_q_b[11]_clock_0, , , );
G1_q_b[11]_PORT_B_address = BUS(rdaddress[0], rdaddress[1], rdaddress[2], rdaddress[3], rdaddress[4]);
G1_q_b[11]_PORT_B_address_reg = DFFE(G1_q_b[11]_PORT_B_address, G1_q_b[11]_clock_0, , , );
G1_q_b[11]_PORT_A_write_enable = wren;
G1_q_b[11]_PORT_A_write_enable_reg = DFFE(G1_q_b[11]_PORT_A_write_enable, G1_q_b[11]_clock_0, , , );
G1_q_b[11]_PORT_B_read_enable = VCC;
G1_q_b[11]_PORT_B_read_enable_reg = DFFE(G1_q_b[11]_PORT_B_read_enable, G1_q_b[11]_clock_0, , , );
G1_q_b[11]_clock_0 = clk1;
G1_q_b[11]_PORT_B_data_out = MEMORY(G1_q_b[11]_PORT_A_data_in_reg, , G1_q_b[11]_PORT_A_address_reg, G1_q_b[11]_PORT_B_address_reg, G1_q_b[11]_PORT_A_write_enable_reg, G1_q_b[11]_PORT_B_read_enable_reg, , , G1_q_b[11]_clock_0, , , , , );
G1_q_b[11] = G1_q_b[11]_PORT_B_data_out[0];


--G1_q_b[10] is lpm_ram_dp0:inst1|altsyncram:altsyncram_component|altsyncram_g691:auto_generated|q_b[10]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
G1_q_b[10]_PORT_A_data_in = E1_result[10];
G1_q_b[10]_PORT_A_data_in_reg = DFFE(G1_q_b[10]_PORT_A_data_in, G1_q_b[10]_clock_0, , , );
G1_q_b[10]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[10]_PORT_A_address_reg = DFFE(G1_q_b[10]_PORT_A_address, G1_q_b[10]_clock_0, , , );
G1_q_b[10]_PORT_B_address = BUS(rdaddress[0], rdaddress[1], rdaddress[2], rdaddress[3], rdaddress[4]);
G1_q_b[10]_PORT_B_address_reg = DFFE(G1_q_b[10]_PORT_B_address, G1_q_b[10]_clock_0, , , );
G1_q_b[10]_PORT_A_write_enable = wren;
G1_q_b[10]_PORT_A_write_enable_reg = DFFE(G1_q_b[10]_PORT_A_write_enable, G1_q_b[10]_clock_0, , , );
G1_q_b[10]_PORT_B_read_enable = VCC;
G1_q_b[10]_PORT_B_read_enable_reg = DFFE(G1_q_b[10]_PORT_B_read_enable, G1_q_b[10]_clock_0, , , );
G1_q_b[10]_clock_0 = clk1;
G1_q_b[10]_PORT_B_data_out = MEMORY(G1_q_b[10]_PORT_A_data_in_reg, , G1_q_b[10]_PORT_A_address_reg, G1_q_b[10]_PORT_B_address_reg, G1_q_b[10]_PORT_A_write_enable_reg, G1_q_b[10]_PORT_B_read_enable_reg, , , G1_q_b[10]_clock_0, , , , , );
G1_q_b[10] = G1_q_b[10]_PORT_B_data_out[0];


--G1_q_b[9] is lpm_ram_dp0:inst1|altsyncram:altsyncram_component|altsyncram_g691:auto_generated|q_b[9]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
G1_q_b[9]_PORT_A_data_in = E1_result[9];
G1_q_b[9]_PORT_A_data_in_reg = DFFE(G1_q_b[9]_PORT_A_data_in, G1_q_b[9]_clock_0, , , );
G1_q_b[9]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[9]_PORT_A_address_reg = DFFE(G1_q_b[9]_PORT_A_address, G1_q_b[9]_clock_0, , , );
G1_q_b[9]_PORT_B_address = BUS(rdaddress[0], rdaddress[1], rdaddress[2], rdaddress[3], rdaddress[4]);
G1_q_b[9]_PORT_B_address_reg = DFFE(G1_q_b[9]_PORT_B_address, G1_q_b[9]_clock_0, , , );
G1_q_b[9]_PORT_A_write_enable = wren;
G1_q_b[9]_PORT_A_write_enable_reg = DFFE(G1_q_b[9]_PORT_A_write_enable, G1_q_b[9]_clock_0, , , );
G1_q_b[9]_PORT_B_read_enable = VCC;
G1_q_b[9]_PORT_B_read_enable_reg = DFFE(G1_q_b[9]_PORT_B_read_enable, G1_q_b[9]_clock_0, , , );
G1_q_b[9]_clock_0 = clk1;
G1_q_b[9]_PORT_B_data_out = MEMORY(G1_q_b[9]_PORT_A_data_in_reg, , G1_q_b[9]_PORT_A_address_reg, G1_q_b[9]_PORT_B_address_reg, G1_q_b[9]_PORT_A_write_enable_reg, G1_q_b[9]_PORT_B_read_enable_reg, , , G1_q_b[9]_clock_0, , , , , );
G1_q_b[9] = G1_q_b[9]_PORT_B_data_out[0];


--G1_q_b[8] is lpm_ram_dp0:inst1|altsyncram:altsyncram_component|altsyncram_g691:auto_generated|q_b[8]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
G1_q_b[8]_PORT_A_data_in = E1_result[8];
G1_q_b[8]_PORT_A_data_in_reg = DFFE(G1_q_b[8]_PORT_A_data_in, G1_q_b[8]_clock_0, , , );
G1_q_b[8]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[8]_PORT_A_address_reg = DFFE(G1_q_b[8]_PORT_A_address, G1_q_b[8]_clock_0, , , );
G1_q_b[8]_PORT_B_address = BUS(rdaddress[0], rdaddress[1], rdaddress[2], rdaddress[3], rdaddress[4]);
G1_q_b[8]_PORT_B_address_reg = DFFE(G1_q_b[8]_PORT_B_address, G1_q_b[8]_clock_0, , , );
G1_q_b[8]_PORT_A_write_enable = wren;
G1_q_b[8]_PORT_A_write_enable_reg = DFFE(G1_q_b[8]_PORT_A_write_enable, G1_q_b[8]_clock_0, , , );
G1_q_b[8]_PORT_B_read_enable = VCC;
G1_q_b[8]_PORT_B_read_enable_reg = DFFE(G1_q_b[8]_PORT_B_read_enable, G1_q_b[8]_clock_0, , , );
G1_q_b[8]_clock_0 = clk1;
G1_q_b[8]_PORT_B_data_out = MEMORY(G1_q_b[8]_PORT_A_data_in_reg, , G1_q_b[8]_PORT_A_address_reg, G1_q_b[8]_PORT_B_address_reg, G1_q_b[8]_PORT_A_write_enable_reg, G1_q_b[8]_PORT_B_read_enable_reg, , , G1_q_b[8]_clock_0, , , , , );
G1_q_b[8] = G1_q_b[8]_PORT_B_data_out[0];


--G1_q_b[7] is lpm_ram_dp0:inst1|altsyncram:altsyncram_component|altsyncram_g691:auto_generated|q_b[7]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
G1_q_b[7]_PORT_A_data_in = E1_result[7];
G1_q_b[7]_PORT_A_data_in_reg = DFFE(G1_q_b[7]_PORT_A_data_in, G1_q_b[7]_clock_0, , , );
G1_q_b[7]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[7]_PORT_A_address_reg = DFFE(G1_q_b[7]_PORT_A_address, G1_q_b[7]_clock_0, , , );
G1_q_b[7]_PORT_B_address = BUS(rdaddress[0], rdaddress[1], rdaddress[2], rdaddress[3], rdaddress[4]);
G1_q_b[7]_PORT_B_address_reg = DFFE(G1_q_b[7]_PORT_B_address, G1_q_b[7]_clock_0, , , );
G1_q_b[7]_PORT_A_write_enable = wren;
G1_q_b[7]_PORT_A_write_enable_reg = DFFE(G1_q_b[7]_PORT_A_write_enable, G1_q_b[7]_clock_0, , , );
G1_q_b[7]_PORT_B_read_enable = VCC;
G1_q_b[7]_PORT_B_read_enable_reg = DFFE(G1_q_b[7]_PORT_B_read_enable, G1_q_b[7]_clock_0, , , );
G1_q_b[7]_clock_0 = clk1;
G1_q_b[7]_PORT_B_data_out = MEMORY(G1_q_b[7]_PORT_A_data_in_reg, , G1_q_b[7]_PORT_A_address_reg, G1_q_b[7]_PORT_B_address_reg, G1_q_b[7]_PORT_A_write_enable_reg, G1_q_b[7]_PORT_B_read_enable_reg, , , G1_q_b[7]_clock_0, , , , , );
G1_q_b[7] = G1_q_b[7]_PORT_B_data_out[0];


--G1_q_b[6] is lpm_ram_dp0:inst1|altsyncram:altsyncram_component|altsyncram_g691:auto_generated|q_b[6]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
G1_q_b[6]_PORT_A_data_in = E1_result[6];
G1_q_b[6]_PORT_A_data_in_reg = DFFE(G1_q_b[6]_PORT_A_data_in, G1_q_b[6]_clock_0, , , );
G1_q_b[6]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[6]_PORT_A_address_reg = DFFE(G1_q_b[6]_PORT_A_address, G1_q_b[6]_clock_0, , , );
G1_q_b[6]_PORT_B_address = BUS(rdaddress[0], rdaddress[1], rdaddress[2], rdaddress[3], rdaddress[4]);
G1_q_b[6]_PORT_B_address_reg = DFFE(G1_q_b[6]_PORT_B_address, G1_q_b[6]_clock_0, , , );
G1_q_b[6]_PORT_A_write_enable = wren;
G1_q_b[6]_PORT_A_write_enable_reg = DFFE(G1_q_b[6]_PORT_A_write_enable, G1_q_b[6]_clock_0, , , );
G1_q_b[6]_PORT_B_read_enable = VCC;
G1_q_b[6]_PORT_B_read_enable_reg = DFFE(G1_q_b[6]_PORT_B_read_enable, G1_q_b[6]_clock_0, , , );
G1_q_b[6]_clock_0 = clk1;
G1_q_b[6]_PORT_B_data_out = MEMORY(G1_q_b[6]_PORT_A_data_in_reg, , G1_q_b[6]_PORT_A_address_reg, G1_q_b[6]_PORT_B_address_reg, G1_q_b[6]_PORT_A_write_enable_reg, G1_q_b[6]_PORT_B_read_enable_reg, , , G1_q_b[6]_clock_0, , , , , );
G1_q_b[6] = G1_q_b[6]_PORT_B_data_out[0];


--G1_q_b[5] is lpm_ram_dp0:inst1|altsyncram:altsyncram_component|altsyncram_g691:auto_generated|q_b[5]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
G1_q_b[5]_PORT_A_data_in = E1_result[5];
G1_q_b[5]_PORT_A_data_in_reg = DFFE(G1_q_b[5]_PORT_A_data_in, G1_q_b[5]_clock_0, , , );
G1_q_b[5]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[5]_PORT_A_address_reg = DFFE(G1_q_b[5]_PORT_A_address, G1_q_b[5]_clock_0, , , );
G1_q_b[5]_PORT_B_address = BUS(rdaddress[0], rdaddress[1], rdaddress[2], rdaddress[3], rdaddress[4]);
G1_q_b[5]_PORT_B_address_reg = DFFE(G1_q_b[5]_PORT_B_address, G1_q_b[5]_clock_0, , , );
G1_q_b[5]_PORT_A_write_enable = wren;
G1_q_b[5]_PORT_A_write_enable_reg = DFFE(G1_q_b[5]_PORT_A_write_enable, G1_q_b[5]_clock_0, , , );
G1_q_b[5]_PORT_B_read_enable = VCC;
G1_q_b[5]_PORT_B_read_enable_reg = DFFE(G1_q_b[5]_PORT_B_read_enable, G1_q_b[5]_clock_0, , , );
G1_q_b[5]_clock_0 = clk1;
G1_q_b[5]_PORT_B_data_out = MEMORY(G1_q_b[5]_PORT_A_data_in_reg, , G1_q_b[5]_PORT_A_address_reg, G1_q_b[5]_PORT_B_address_reg, G1_q_b[5]_PORT_A_write_enable_reg, G1_q_b[5]_PORT_B_read_enable_reg, , , G1_q_b[5]_clock_0, , , , , );
G1_q_b[5] = G1_q_b[5]_PORT_B_data_out[0];


--G1_q_b[4] is lpm_ram_dp0:inst1|altsyncram:altsyncram_component|altsyncram_g691:auto_generated|q_b[4]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
G1_q_b[4]_PORT_A_data_in = E1_result[4];
G1_q_b[4]_PORT_A_data_in_reg = DFFE(G1_q_b[4]_PORT_A_data_in, G1_q_b[4]_clock_0, , , );
G1_q_b[4]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[4]_PORT_A_address_reg = DFFE(G1_q_b[4]_PORT_A_address, G1_q_b[4]_clock_0, , , );
G1_q_b[4]_PORT_B_address = BUS(rdaddress[0], rdaddress[1], rdaddress[2], rdaddress[3], rdaddress[4]);
G1_q_b[4]_PORT_B_address_reg = DFFE(G1_q_b[4]_PORT_B_address, G1_q_b[4]_clock_0, , , );