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📄 pipemult.fit.eqn

📁 该源码实现了一个8*8位的乘法器
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--G1_q_b[15] is lpm_ram_dp0:inst1|altsyncram:altsyncram_component|altsyncram_g691:auto_generated|q_b[15] at M512_X4_Y8
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 16, Port B Depth: 32, Port B Width: 16
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
G1_q_b[15]_PORT_A_data_in = BUS(E1_result[15], E1_result[14], E1_result[13], E1_result[12], E1_result[11], E1_result[10], E1_result[9], E1_result[8], E1_result[7], E1_result[6], E1_result[5], E1_result[4], E1_result[3], E1_result[2], E1_result[1], E1_result[0]);
G1_q_b[15]_PORT_A_data_in_reg = DFFE(G1_q_b[15]_PORT_A_data_in, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[15]_PORT_A_address_reg = DFFE(G1_q_b[15]_PORT_A_address, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_B_address = BUS(rdaddress[0], rdaddress[1], rdaddress[2], rdaddress[3], rdaddress[4]);
G1_q_b[15]_PORT_B_address_reg = DFFE(G1_q_b[15]_PORT_B_address, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_A_write_enable = wren;
G1_q_b[15]_PORT_A_write_enable_reg = DFFE(G1_q_b[15]_PORT_A_write_enable, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_B_read_enable = VCC;
G1_q_b[15]_PORT_B_read_enable_reg = DFFE(G1_q_b[15]_PORT_B_read_enable, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_clock_0 = GLOBAL(clk1);
G1_q_b[15]_PORT_B_data_out = MEMORY(G1_q_b[15]_PORT_A_data_in_reg, , G1_q_b[15]_PORT_A_address_reg, G1_q_b[15]_PORT_B_address_reg, G1_q_b[15]_PORT_A_write_enable_reg, G1_q_b[15]_PORT_B_read_enable_reg, , , G1_q_b[15]_clock_0, , , , , );
G1_q_b[15] = G1_q_b[15]_PORT_B_data_out[0];

--G1_q_b[0] is lpm_ram_dp0:inst1|altsyncram:altsyncram_component|altsyncram_g691:auto_generated|q_b[0] at M512_X4_Y8
G1_q_b[15]_PORT_A_data_in = BUS(E1_result[15], E1_result[14], E1_result[13], E1_result[12], E1_result[11], E1_result[10], E1_result[9], E1_result[8], E1_result[7], E1_result[6], E1_result[5], E1_result[4], E1_result[3], E1_result[2], E1_result[1], E1_result[0]);
G1_q_b[15]_PORT_A_data_in_reg = DFFE(G1_q_b[15]_PORT_A_data_in, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[15]_PORT_A_address_reg = DFFE(G1_q_b[15]_PORT_A_address, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_B_address = BUS(rdaddress[0], rdaddress[1], rdaddress[2], rdaddress[3], rdaddress[4]);
G1_q_b[15]_PORT_B_address_reg = DFFE(G1_q_b[15]_PORT_B_address, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_A_write_enable = wren;
G1_q_b[15]_PORT_A_write_enable_reg = DFFE(G1_q_b[15]_PORT_A_write_enable, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_B_read_enable = VCC;
G1_q_b[15]_PORT_B_read_enable_reg = DFFE(G1_q_b[15]_PORT_B_read_enable, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_clock_0 = GLOBAL(clk1);
G1_q_b[15]_PORT_B_data_out = MEMORY(G1_q_b[15]_PORT_A_data_in_reg, , G1_q_b[15]_PORT_A_address_reg, G1_q_b[15]_PORT_B_address_reg, G1_q_b[15]_PORT_A_write_enable_reg, G1_q_b[15]_PORT_B_read_enable_reg, , , G1_q_b[15]_clock_0, , , , , );
G1_q_b[0] = G1_q_b[15]_PORT_B_data_out[15];

--G1_q_b[1] is lpm_ram_dp0:inst1|altsyncram:altsyncram_component|altsyncram_g691:auto_generated|q_b[1] at M512_X4_Y8
G1_q_b[15]_PORT_A_data_in = BUS(E1_result[15], E1_result[14], E1_result[13], E1_result[12], E1_result[11], E1_result[10], E1_result[9], E1_result[8], E1_result[7], E1_result[6], E1_result[5], E1_result[4], E1_result[3], E1_result[2], E1_result[1], E1_result[0]);
G1_q_b[15]_PORT_A_data_in_reg = DFFE(G1_q_b[15]_PORT_A_data_in, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[15]_PORT_A_address_reg = DFFE(G1_q_b[15]_PORT_A_address, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_B_address = BUS(rdaddress[0], rdaddress[1], rdaddress[2], rdaddress[3], rdaddress[4]);
G1_q_b[15]_PORT_B_address_reg = DFFE(G1_q_b[15]_PORT_B_address, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_A_write_enable = wren;
G1_q_b[15]_PORT_A_write_enable_reg = DFFE(G1_q_b[15]_PORT_A_write_enable, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_B_read_enable = VCC;
G1_q_b[15]_PORT_B_read_enable_reg = DFFE(G1_q_b[15]_PORT_B_read_enable, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_clock_0 = GLOBAL(clk1);
G1_q_b[15]_PORT_B_data_out = MEMORY(G1_q_b[15]_PORT_A_data_in_reg, , G1_q_b[15]_PORT_A_address_reg, G1_q_b[15]_PORT_B_address_reg, G1_q_b[15]_PORT_A_write_enable_reg, G1_q_b[15]_PORT_B_read_enable_reg, , , G1_q_b[15]_clock_0, , , , , );
G1_q_b[1] = G1_q_b[15]_PORT_B_data_out[14];

--G1_q_b[2] is lpm_ram_dp0:inst1|altsyncram:altsyncram_component|altsyncram_g691:auto_generated|q_b[2] at M512_X4_Y8
G1_q_b[15]_PORT_A_data_in = BUS(E1_result[15], E1_result[14], E1_result[13], E1_result[12], E1_result[11], E1_result[10], E1_result[9], E1_result[8], E1_result[7], E1_result[6], E1_result[5], E1_result[4], E1_result[3], E1_result[2], E1_result[1], E1_result[0]);
G1_q_b[15]_PORT_A_data_in_reg = DFFE(G1_q_b[15]_PORT_A_data_in, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[15]_PORT_A_address_reg = DFFE(G1_q_b[15]_PORT_A_address, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_B_address = BUS(rdaddress[0], rdaddress[1], rdaddress[2], rdaddress[3], rdaddress[4]);
G1_q_b[15]_PORT_B_address_reg = DFFE(G1_q_b[15]_PORT_B_address, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_A_write_enable = wren;
G1_q_b[15]_PORT_A_write_enable_reg = DFFE(G1_q_b[15]_PORT_A_write_enable, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_B_read_enable = VCC;
G1_q_b[15]_PORT_B_read_enable_reg = DFFE(G1_q_b[15]_PORT_B_read_enable, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_clock_0 = GLOBAL(clk1);
G1_q_b[15]_PORT_B_data_out = MEMORY(G1_q_b[15]_PORT_A_data_in_reg, , G1_q_b[15]_PORT_A_address_reg, G1_q_b[15]_PORT_B_address_reg, G1_q_b[15]_PORT_A_write_enable_reg, G1_q_b[15]_PORT_B_read_enable_reg, , , G1_q_b[15]_clock_0, , , , , );
G1_q_b[2] = G1_q_b[15]_PORT_B_data_out[13];

--G1_q_b[3] is lpm_ram_dp0:inst1|altsyncram:altsyncram_component|altsyncram_g691:auto_generated|q_b[3] at M512_X4_Y8
G1_q_b[15]_PORT_A_data_in = BUS(E1_result[15], E1_result[14], E1_result[13], E1_result[12], E1_result[11], E1_result[10], E1_result[9], E1_result[8], E1_result[7], E1_result[6], E1_result[5], E1_result[4], E1_result[3], E1_result[2], E1_result[1], E1_result[0]);
G1_q_b[15]_PORT_A_data_in_reg = DFFE(G1_q_b[15]_PORT_A_data_in, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[15]_PORT_A_address_reg = DFFE(G1_q_b[15]_PORT_A_address, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_B_address = BUS(rdaddress[0], rdaddress[1], rdaddress[2], rdaddress[3], rdaddress[4]);
G1_q_b[15]_PORT_B_address_reg = DFFE(G1_q_b[15]_PORT_B_address, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_A_write_enable = wren;
G1_q_b[15]_PORT_A_write_enable_reg = DFFE(G1_q_b[15]_PORT_A_write_enable, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_B_read_enable = VCC;
G1_q_b[15]_PORT_B_read_enable_reg = DFFE(G1_q_b[15]_PORT_B_read_enable, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_clock_0 = GLOBAL(clk1);
G1_q_b[15]_PORT_B_data_out = MEMORY(G1_q_b[15]_PORT_A_data_in_reg, , G1_q_b[15]_PORT_A_address_reg, G1_q_b[15]_PORT_B_address_reg, G1_q_b[15]_PORT_A_write_enable_reg, G1_q_b[15]_PORT_B_read_enable_reg, , , G1_q_b[15]_clock_0, , , , , );
G1_q_b[3] = G1_q_b[15]_PORT_B_data_out[12];

--G1_q_b[4] is lpm_ram_dp0:inst1|altsyncram:altsyncram_component|altsyncram_g691:auto_generated|q_b[4] at M512_X4_Y8
G1_q_b[15]_PORT_A_data_in = BUS(E1_result[15], E1_result[14], E1_result[13], E1_result[12], E1_result[11], E1_result[10], E1_result[9], E1_result[8], E1_result[7], E1_result[6], E1_result[5], E1_result[4], E1_result[3], E1_result[2], E1_result[1], E1_result[0]);
G1_q_b[15]_PORT_A_data_in_reg = DFFE(G1_q_b[15]_PORT_A_data_in, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[15]_PORT_A_address_reg = DFFE(G1_q_b[15]_PORT_A_address, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_B_address = BUS(rdaddress[0], rdaddress[1], rdaddress[2], rdaddress[3], rdaddress[4]);
G1_q_b[15]_PORT_B_address_reg = DFFE(G1_q_b[15]_PORT_B_address, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_A_write_enable = wren;
G1_q_b[15]_PORT_A_write_enable_reg = DFFE(G1_q_b[15]_PORT_A_write_enable, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_B_read_enable = VCC;
G1_q_b[15]_PORT_B_read_enable_reg = DFFE(G1_q_b[15]_PORT_B_read_enable, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_clock_0 = GLOBAL(clk1);
G1_q_b[15]_PORT_B_data_out = MEMORY(G1_q_b[15]_PORT_A_data_in_reg, , G1_q_b[15]_PORT_A_address_reg, G1_q_b[15]_PORT_B_address_reg, G1_q_b[15]_PORT_A_write_enable_reg, G1_q_b[15]_PORT_B_read_enable_reg, , , G1_q_b[15]_clock_0, , , , , );
G1_q_b[4] = G1_q_b[15]_PORT_B_data_out[11];

--G1_q_b[5] is lpm_ram_dp0:inst1|altsyncram:altsyncram_component|altsyncram_g691:auto_generated|q_b[5] at M512_X4_Y8
G1_q_b[15]_PORT_A_data_in = BUS(E1_result[15], E1_result[14], E1_result[13], E1_result[12], E1_result[11], E1_result[10], E1_result[9], E1_result[8], E1_result[7], E1_result[6], E1_result[5], E1_result[4], E1_result[3], E1_result[2], E1_result[1], E1_result[0]);
G1_q_b[15]_PORT_A_data_in_reg = DFFE(G1_q_b[15]_PORT_A_data_in, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[15]_PORT_A_address_reg = DFFE(G1_q_b[15]_PORT_A_address, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_B_address = BUS(rdaddress[0], rdaddress[1], rdaddress[2], rdaddress[3], rdaddress[4]);
G1_q_b[15]_PORT_B_address_reg = DFFE(G1_q_b[15]_PORT_B_address, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_A_write_enable = wren;
G1_q_b[15]_PORT_A_write_enable_reg = DFFE(G1_q_b[15]_PORT_A_write_enable, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_B_read_enable = VCC;
G1_q_b[15]_PORT_B_read_enable_reg = DFFE(G1_q_b[15]_PORT_B_read_enable, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_clock_0 = GLOBAL(clk1);
G1_q_b[15]_PORT_B_data_out = MEMORY(G1_q_b[15]_PORT_A_data_in_reg, , G1_q_b[15]_PORT_A_address_reg, G1_q_b[15]_PORT_B_address_reg, G1_q_b[15]_PORT_A_write_enable_reg, G1_q_b[15]_PORT_B_read_enable_reg, , , G1_q_b[15]_clock_0, , , , , );
G1_q_b[5] = G1_q_b[15]_PORT_B_data_out[10];

--G1_q_b[6] is lpm_ram_dp0:inst1|altsyncram:altsyncram_component|altsyncram_g691:auto_generated|q_b[6] at M512_X4_Y8
G1_q_b[15]_PORT_A_data_in = BUS(E1_result[15], E1_result[14], E1_result[13], E1_result[12], E1_result[11], E1_result[10], E1_result[9], E1_result[8], E1_result[7], E1_result[6], E1_result[5], E1_result[4], E1_result[3], E1_result[2], E1_result[1], E1_result[0]);
G1_q_b[15]_PORT_A_data_in_reg = DFFE(G1_q_b[15]_PORT_A_data_in, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[15]_PORT_A_address_reg = DFFE(G1_q_b[15]_PORT_A_address, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_B_address = BUS(rdaddress[0], rdaddress[1], rdaddress[2], rdaddress[3], rdaddress[4]);
G1_q_b[15]_PORT_B_address_reg = DFFE(G1_q_b[15]_PORT_B_address, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_A_write_enable = wren;
G1_q_b[15]_PORT_A_write_enable_reg = DFFE(G1_q_b[15]_PORT_A_write_enable, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_B_read_enable = VCC;
G1_q_b[15]_PORT_B_read_enable_reg = DFFE(G1_q_b[15]_PORT_B_read_enable, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_clock_0 = GLOBAL(clk1);
G1_q_b[15]_PORT_B_data_out = MEMORY(G1_q_b[15]_PORT_A_data_in_reg, , G1_q_b[15]_PORT_A_address_reg, G1_q_b[15]_PORT_B_address_reg, G1_q_b[15]_PORT_A_write_enable_reg, G1_q_b[15]_PORT_B_read_enable_reg, , , G1_q_b[15]_clock_0, , , , , );
G1_q_b[6] = G1_q_b[15]_PORT_B_data_out[9];

--G1_q_b[7] is lpm_ram_dp0:inst1|altsyncram:altsyncram_component|altsyncram_g691:auto_generated|q_b[7] at M512_X4_Y8
G1_q_b[15]_PORT_A_data_in = BUS(E1_result[15], E1_result[14], E1_result[13], E1_result[12], E1_result[11], E1_result[10], E1_result[9], E1_result[8], E1_result[7], E1_result[6], E1_result[5], E1_result[4], E1_result[3], E1_result[2], E1_result[1], E1_result[0]);
G1_q_b[15]_PORT_A_data_in_reg = DFFE(G1_q_b[15]_PORT_A_data_in, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[15]_PORT_A_address_reg = DFFE(G1_q_b[15]_PORT_A_address, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_B_address = BUS(rdaddress[0], rdaddress[1], rdaddress[2], rdaddress[3], rdaddress[4]);
G1_q_b[15]_PORT_B_address_reg = DFFE(G1_q_b[15]_PORT_B_address, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_A_write_enable = wren;
G1_q_b[15]_PORT_A_write_enable_reg = DFFE(G1_q_b[15]_PORT_A_write_enable, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_B_read_enable = VCC;
G1_q_b[15]_PORT_B_read_enable_reg = DFFE(G1_q_b[15]_PORT_B_read_enable, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_clock_0 = GLOBAL(clk1);
G1_q_b[15]_PORT_B_data_out = MEMORY(G1_q_b[15]_PORT_A_data_in_reg, , G1_q_b[15]_PORT_A_address_reg, G1_q_b[15]_PORT_B_address_reg, G1_q_b[15]_PORT_A_write_enable_reg, G1_q_b[15]_PORT_B_read_enable_reg, , , G1_q_b[15]_clock_0, , , , , );
G1_q_b[7] = G1_q_b[15]_PORT_B_data_out[8];

--G1_q_b[8] is lpm_ram_dp0:inst1|altsyncram:altsyncram_component|altsyncram_g691:auto_generated|q_b[8] at M512_X4_Y8
G1_q_b[15]_PORT_A_data_in = BUS(E1_result[15], E1_result[14], E1_result[13], E1_result[12], E1_result[11], E1_result[10], E1_result[9], E1_result[8], E1_result[7], E1_result[6], E1_result[5], E1_result[4], E1_result[3], E1_result[2], E1_result[1], E1_result[0]);
G1_q_b[15]_PORT_A_data_in_reg = DFFE(G1_q_b[15]_PORT_A_data_in, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[15]_PORT_A_address_reg = DFFE(G1_q_b[15]_PORT_A_address, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_B_address = BUS(rdaddress[0], rdaddress[1], rdaddress[2], rdaddress[3], rdaddress[4]);
G1_q_b[15]_PORT_B_address_reg = DFFE(G1_q_b[15]_PORT_B_address, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_A_write_enable = wren;
G1_q_b[15]_PORT_A_write_enable_reg = DFFE(G1_q_b[15]_PORT_A_write_enable, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_B_read_enable = VCC;
G1_q_b[15]_PORT_B_read_enable_reg = DFFE(G1_q_b[15]_PORT_B_read_enable, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_clock_0 = GLOBAL(clk1);
G1_q_b[15]_PORT_B_data_out = MEMORY(G1_q_b[15]_PORT_A_data_in_reg, , G1_q_b[15]_PORT_A_address_reg, G1_q_b[15]_PORT_B_address_reg, G1_q_b[15]_PORT_A_write_enable_reg, G1_q_b[15]_PORT_B_read_enable_reg, , , G1_q_b[15]_clock_0, , , , , );
G1_q_b[8] = G1_q_b[15]_PORT_B_data_out[7];

--G1_q_b[9] is lpm_ram_dp0:inst1|altsyncram:altsyncram_component|altsyncram_g691:auto_generated|q_b[9] at M512_X4_Y8
G1_q_b[15]_PORT_A_data_in = BUS(E1_result[15], E1_result[14], E1_result[13], E1_result[12], E1_result[11], E1_result[10], E1_result[9], E1_result[8], E1_result[7], E1_result[6], E1_result[5], E1_result[4], E1_result[3], E1_result[2], E1_result[1], E1_result[0]);
G1_q_b[15]_PORT_A_data_in_reg = DFFE(G1_q_b[15]_PORT_A_data_in, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[15]_PORT_A_address_reg = DFFE(G1_q_b[15]_PORT_A_address, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_B_address = BUS(rdaddress[0], rdaddress[1], rdaddress[2], rdaddress[3], rdaddress[4]);
G1_q_b[15]_PORT_B_address_reg = DFFE(G1_q_b[15]_PORT_B_address, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_A_write_enable = wren;
G1_q_b[15]_PORT_A_write_enable_reg = DFFE(G1_q_b[15]_PORT_A_write_enable, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_B_read_enable = VCC;
G1_q_b[15]_PORT_B_read_enable_reg = DFFE(G1_q_b[15]_PORT_B_read_enable, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_clock_0 = GLOBAL(clk1);
G1_q_b[15]_PORT_B_data_out = MEMORY(G1_q_b[15]_PORT_A_data_in_reg, , G1_q_b[15]_PORT_A_address_reg, G1_q_b[15]_PORT_B_address_reg, G1_q_b[15]_PORT_A_write_enable_reg, G1_q_b[15]_PORT_B_read_enable_reg, , , G1_q_b[15]_clock_0, , , , , );
G1_q_b[9] = G1_q_b[15]_PORT_B_data_out[6];

--G1_q_b[10] is lpm_ram_dp0:inst1|altsyncram:altsyncram_component|altsyncram_g691:auto_generated|q_b[10] at M512_X4_Y8
G1_q_b[15]_PORT_A_data_in = BUS(E1_result[15], E1_result[14], E1_result[13], E1_result[12], E1_result[11], E1_result[10], E1_result[9], E1_result[8], E1_result[7], E1_result[6], E1_result[5], E1_result[4], E1_result[3], E1_result[2], E1_result[1], E1_result[0]);
G1_q_b[15]_PORT_A_data_in_reg = DFFE(G1_q_b[15]_PORT_A_data_in, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[15]_PORT_A_address_reg = DFFE(G1_q_b[15]_PORT_A_address, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_B_address = BUS(rdaddress[0], rdaddress[1], rdaddress[2], rdaddress[3], rdaddress[4]);
G1_q_b[15]_PORT_B_address_reg = DFFE(G1_q_b[15]_PORT_B_address, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_A_write_enable = wren;
G1_q_b[15]_PORT_A_write_enable_reg = DFFE(G1_q_b[15]_PORT_A_write_enable, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_B_read_enable = VCC;
G1_q_b[15]_PORT_B_read_enable_reg = DFFE(G1_q_b[15]_PORT_B_read_enable, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_clock_0 = GLOBAL(clk1);
G1_q_b[15]_PORT_B_data_out = MEMORY(G1_q_b[15]_PORT_A_data_in_reg, , G1_q_b[15]_PORT_A_address_reg, G1_q_b[15]_PORT_B_address_reg, G1_q_b[15]_PORT_A_write_enable_reg, G1_q_b[15]_PORT_B_read_enable_reg, , , G1_q_b[15]_clock_0, , , , , );
G1_q_b[10] = G1_q_b[15]_PORT_B_data_out[5];

--G1_q_b[11] is lpm_ram_dp0:inst1|altsyncram:altsyncram_component|altsyncram_g691:auto_generated|q_b[11] at M512_X4_Y8
G1_q_b[15]_PORT_A_data_in = BUS(E1_result[15], E1_result[14], E1_result[13], E1_result[12], E1_result[11], E1_result[10], E1_result[9], E1_result[8], E1_result[7], E1_result[6], E1_result[5], E1_result[4], E1_result[3], E1_result[2], E1_result[1], E1_result[0]);
G1_q_b[15]_PORT_A_data_in_reg = DFFE(G1_q_b[15]_PORT_A_data_in, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[15]_PORT_A_address_reg = DFFE(G1_q_b[15]_PORT_A_address, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_B_address = BUS(rdaddress[0], rdaddress[1], rdaddress[2], rdaddress[3], rdaddress[4]);
G1_q_b[15]_PORT_B_address_reg = DFFE(G1_q_b[15]_PORT_B_address, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_A_write_enable = wren;
G1_q_b[15]_PORT_A_write_enable_reg = DFFE(G1_q_b[15]_PORT_A_write_enable, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_B_read_enable = VCC;
G1_q_b[15]_PORT_B_read_enable_reg = DFFE(G1_q_b[15]_PORT_B_read_enable, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_clock_0 = GLOBAL(clk1);
G1_q_b[15]_PORT_B_data_out = MEMORY(G1_q_b[15]_PORT_A_data_in_reg, , G1_q_b[15]_PORT_A_address_reg, G1_q_b[15]_PORT_B_address_reg, G1_q_b[15]_PORT_A_write_enable_reg, G1_q_b[15]_PORT_B_read_enable_reg, , , G1_q_b[15]_clock_0, , , , , );
G1_q_b[11] = G1_q_b[15]_PORT_B_data_out[4];

--G1_q_b[12] is lpm_ram_dp0:inst1|altsyncram:altsyncram_component|altsyncram_g691:auto_generated|q_b[12] at M512_X4_Y8
G1_q_b[15]_PORT_A_data_in = BUS(E1_result[15], E1_result[14], E1_result[13], E1_result[12], E1_result[11], E1_result[10], E1_result[9], E1_result[8], E1_result[7], E1_result[6], E1_result[5], E1_result[4], E1_result[3], E1_result[2], E1_result[1], E1_result[0]);
G1_q_b[15]_PORT_A_data_in_reg = DFFE(G1_q_b[15]_PORT_A_data_in, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[15]_PORT_A_address_reg = DFFE(G1_q_b[15]_PORT_A_address, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_B_address = BUS(rdaddress[0], rdaddress[1], rdaddress[2], rdaddress[3], rdaddress[4]);
G1_q_b[15]_PORT_B_address_reg = DFFE(G1_q_b[15]_PORT_B_address, G1_q_b[15]_clock_0, , , );
G1_q_b[15]_PORT_A_write_enable = wren;
G1_q_b[15]_PORT_A_write_enable_reg = DFFE(G1_q_b[15]_PORT_A_write_enable, G1_q_b[15]_clock_0, , , );
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