pl_fsk.fit.summary

数字通信系统通信系统调制解调（PL_FSK）VHDL建模

Fitter Status : Successful - Sat Mar 18 11:19:12 2006
Quartus II Version : 5.1 Build 176 10/26/2005 SJ Web Edition
Revision Name : PL_FSK
Top-level Entity Name : PL_FSK
Family : Stratix
Device : EP1S10F484C5
Timing Models : Final
Total logic elements : 17 / 10,570 ( < 1 % )
Total pins : 5 / 336 ( 1 % )
Total virtual pins : 0
Total memory bits : 0 / 920,448 ( 0 % )
DSP block 9-bit elements : 0 / 48 ( 0 % )
Total PLLs : 0 / 6 ( 0 % )
Total DLLs : 0 / 2 ( 0 % )