pl_fsk.map.eqn

数字通信系统通信系统调制解调（PL_FSK）VHDL建模

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--B1_y is PL_FSK1:inst|y
--operation mode is normal

B1_y_lut_out = x & B1_f2 # !x & (B1_f1);
B1_y = DFFEAS(B1_y_lut_out, clk, VCC, , , , , , );


--B1_f2 is PL_FSK1:inst|f2
--operation mode is normal

B1_f2_lut_out = !C1_q1[0];
B1_f2 = DFFEAS(B1_f2_lut_out, clk, VCC, , start, , , , );


--B1_f1 is PL_FSK1:inst|f1
--operation mode is normal

B1_f1_lut_out = A1L5 # B1_f1 & (!A1L4);
B1_f1 = DFFEAS(B1_f1_lut_out, clk, VCC, , start, , , , );


--C1_m[2] is PL_FSK2:inst5|m[2]
--operation mode is normal

C1_m[2]_lut_out = C1_m[2] $ (!A1L3 & C1_m[1] & C1_m[0]);
C1_m[2] = DFFEAS(C1_m[2]_lut_out, C1_xx, !A1L4, , , , , , );


--C1_q1[3] is PL_FSK2:inst5|q1[3]
--operation mode is normal

C1_q1[3]_lut_out = start & !A1L4 & (C1_q1[3] $ C1L1);
C1_q1[3] = DFFEAS(C1_q1[3]_lut_out, clk, VCC, , , , , , );


--C1_q1[1] is PL_FSK2:inst5|q1[1]
--operation mode is normal

C1_q1[1]_lut_out = start & !A1L4 & (C1_q1[0] $ C1_q1[1]);
C1_q1[1] = DFFEAS(C1_q1[1]_lut_out, clk, VCC, , , , , , );


--C1_q1[0] is PL_FSK2:inst5|q1[0]
--operation mode is normal

C1_q1[0]_lut_out = !C1_q1[0] & (start);
C1_q1[0] = DFFEAS(C1_q1[0]_lut_out, clk, VCC, , , , , , );


--C1_q1[2] is PL_FSK2:inst5|q1[2]
--operation mode is normal

C1_q1[2]_lut_out = start & !A1L4 & (C1_q1[2] $ C1L2);
C1_q1[2] = DFFEAS(C1_q1[2]_lut_out, clk, VCC, , , , , , );


--A1L3 is rtl~0
--operation mode is normal

A1L3 = C1_q1[3] & C1_q1[1] & !C1_q1[0] & !C1_q1[2];


--A1L5 is rtl~53
--operation mode is normal

A1L5 = C1_q1[0] & C1_q1[2] & !C1_q1[3] & !C1_q1[1];


--A1L4 is rtl~2
--operation mode is normal

A1L4 = C1_q1[0] & C1_q1[3] & C1_q1[1] & !C1_q1[2];


--C1_m[1] is PL_FSK2:inst5|m[1]
--operation mode is normal

C1_m[1]_lut_out = C1_m[1] $ (!A1L3 & (C1_m[0]));
C1_m[1] = DFFEAS(C1_m[1]_lut_out, C1_xx, !A1L4, , , , , , );


--C1_m[0] is PL_FSK2:inst5|m[0]
--operation mode is normal

C1_m[0]_lut_out = A1L3 $ !C1_m[0];
C1_m[0] = DFFEAS(C1_m[0]_lut_out, C1_xx, !A1L4, , , , , , );


--C1_xx is PL_FSK2:inst5|xx
--operation mode is normal

C1_xx_lut_out = B1_y;
C1_xx = DFFEAS(C1_xx_lut_out, clk, VCC, , , , , , );


--C1L1 is PL_FSK2:inst5|add~142
--operation mode is normal

C1L1 = C1_q1[0] & C1_q1[2] & C1_q1[1];


--C1L2 is PL_FSK2:inst5|add~143
--operation mode is normal

C1L2 = C1_q1[0] & C1_q1[1];


--C1_y is PL_FSK2:inst5|y
--operation mode is normal

C1_y = A1L3 & C1_m[2] # !A1L3 & (C1_y);


--x is x
--operation mode is input

x = INPUT();


--clk is clk
--operation mode is input

clk = INPUT();


--start is start
--operation mode is input

start = INPUT();


--c is c
--operation mode is output

c = OUTPUT(B1_y);


--y is y
--operation mode is output

y = OUTPUT(C1_y);