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📄 fifowr.rpt

📁 这是用AHDL语言编写的一个PCI采集系统的逻辑源码
💻 RPT
📖 第 1 页 / 共 5 页
字号:
   -      7     -    F    02       DFFE   +            0    2    1    1  addr_to_nvsram0
   -      1     -    E    04       DFFE   +            0    2    1    1  addr_to_nvsram1
   -      1     -    F    05       DFFE   +            0    2    1    1  addr_to_nvsram2
   -      4     -    F    05       DFFE   +            0    2    1    1  addr_to_nvsram3
   -      3     -    E    08       DFFE   +            0    2    1    1  addr_to_nvsram4
   -      1     -    E    08       DFFE   +            0    2    1    1  addr_to_nvsram5
   -      3     -    F    09       DFFE   +            0    2    1    1  addr_to_nvsram6
   -      6     -    F    09       DFFE   +            0    2    1    1  addr_to_nvsram7
   -      5     -    F    09       DFFE   +            0    2    1    1  addr_to_nvsram8
   -      2     -    F    11       DFFE   +            0    2    1    1  addr_to_nvsram9
   -      4     -    F    11       DFFE   +            0    2    1    1  addr_to_nvsram10
   -      1     -    F    11       DFFE   +            0    2    1    1  addr_to_nvsram11
   -      5     -    B    14       DFFE   +            0    2    1    1  addr_to_nvsram12
   -      2     -    B    14       DFFE   +            0    2    1    1  addr_to_nvsram13
   -      1     -    F    15       DFFE   +            0    2    1    1  addr_to_nvsram14
   -      4     -    F    15       DFFE   +            0    2    1    1  addr_to_nvsram15
   -      1     -    F    17       DFFE   +            0    2    1    1  addr_to_nvsram16
   -      6     -    F    17       DFFE   +            0    2    0    1  addr_to_nvsram17
   -      7     -    F    17       DFFE   +            0    2    0    1  addr_to_nvsram18
   -      3     -    F    05       DFFE   +            0    2    0    1  addr_to_nvsram19
   -      5     -    F    05       DFFE   +            0    2    0    1  addr_to_nvsram20
   -      7     -    F    05       DFFE   +            0    2    0    1  addr_to_nvsram21
   -      8     -    F    05       DFFE   +            0    2    0    1  addr_to_nvsram22
   -      3     -    F    17       DFFE   +            0    2    0    1  addr_to_nvsram23
   -      3     -    E    04       DFFE   +            0    2    0    1  addr_to_nvsram24
   -      4     -    E    04       DFFE   +            0    2    0    1  addr_to_nvsram25
   -      5     -    E    04       DFFE   +            0    2    0    1  addr_to_nvsram26
   -      2     -    F    02       DFFE   +            0    2    0    1  addr_to_nvsram27
   -      3     -    F    02       DFFE   +            0    2    0    1  addr_to_nvsram28
   -      4     -    F    02       DFFE   +            0    2    0    1  addr_to_nvsram29
   -      4     -    F    17       DFFE   +            0    2    0    1  addr_to_nvsram30
   -      5     -    F    17       DFFE   +            0    2    0    1  addr_to_nvsram31
   -      5     -    D    07       DFFE   +            0    1    1    0  adr2~
   -      2     -    D    13       DFFE   +            0    1    1    0  adr3~
   -      2     -    D    07       DFFE   +            0    1    1    0  adr5~
   -      2     -    A    01       DFFE   +            0    1    0    4  asm_ctrl~1
   -      6     -    A    17       DFFE   +            1    2    0    2  asm_ctrl~2
   -      7     -    A    17       DFFE   +            0    3    0    5  asm_ctrl~3
   -      2     -    A    13       DFFE   +            1    2    0    2  asm_ctrl~4
   -      5     -    A    17       DFFE   +            0    3    0    5  asm_ctrl~5
   -      8     -    A    16       DFFE   +            1    2    0    2  asm_ctrl~6
   -      2     -    A    16       DFFE   +            0    3    0    5  asm_ctrl~7
   -      4     -    A    16       DFFE   +            1    2    0    2  asm_ctrl~8
   -      7     -    A    24       DFFE   +            0    4    0    5  asm_ctrl~9
   -      5     -    A    24       DFFE   +            0    3    0    5  asm_ctrl~10
   -      3     -    A    23       DFFE   +            0    2    0    3  asm_ctrl~11
   -      1     -    A    13       DFFE   +            1    3    0    3  asm_ctrl~12
   -      7     -    A    13       DFFE   +            0    1    0    2  asm_ctrl~13
   -      3     -    D    07       DFFE   +    !       0    3    1    0  /be0~
   -      2     -    D    22       DFFE   +    !       0    3    1    0  /be1~
   -      4     -    D    22       DFFE   +    !       0    3    1    0  /be2~
   -      5     -    D    22       DFFE   +    !       0    3    1    0  /be3~
   -      2     -    D    18      LCELL    s           1    0    1    0  clkout~1
   -      4     -    D    20       DFFE   +            2    2    0    0  data_oe
   -      7     -    E    23       DFFE   +            0    2    1    1  data_to_nvsram0
   -      8     -    E    04       DFFE   +            0    2    1    0  data_to_nvsram1
   -      2     -    E    23       DFFE   +            0    2    1    0  data_to_nvsram2
   -      3     -    E    23       DFFE   +            0    2    1    0  data_to_nvsram3
   -      6     -    E    08       DFFE   +            0    2    1    0  data_to_nvsram4
   -      8     -    E    08       DFFE   +            0    2    1    0  data_to_nvsram5
   -      1     -    F    09       DFFE   +            0    2    1    0  data_to_nvsram6
   -      2     -    F    09       DFFE   +            0    2    1    0  data_to_nvsram7
   -      1     -    A    23       DFFE   +            0    4    0    0  dq_oe
   -      4     -    D    07       DFFE   +    !       0    1    0   36  fifo_oe
   -      2     -    D    20       DFFE   +    !       1    1    1   36  /ptadr~
   -      1     -    D    22       DFFE   +            0    2    0    2  pt_ctrl~1
   -      7     -    D    22       DFFE   +            0    2    0    2  pt_ctrl~2
   -      1     -    E    23       DFFE   +            0    1    0    3  pt_ctrl~3
   -      6     -    D    07       DFFE   +            0    1    0    1  pt_ctrl~4
   -      8     -    E    23       DFFE   +    !       0    2    1    3  /ptrdy~
   -      3     -    D    20       DFFE   +    !       2    1    1   11  /rd~
   -      1     -    A    06       DFFE   +            0    3    1    0  read_data_from_sram0
   -      2     -    A    02       DFFE   +            0    3    1    0  read_data_from_sram1
   -      5     -    A    02       DFFE   +            0    3    1    0  read_data_from_sram2
   -      6     -    A    01       DFFE   +            0    3    1    0  read_data_from_sram3
   -      1     -    A    03       DFFE   +            0    3    1    0  read_data_from_sram4
   -      2     -    A    03       DFFE   +            0    3    1    0  read_data_from_sram5
   -      6     -    A    06       DFFE   +            0    3    1    0  read_data_from_sram6
   -      8     -    A    06       DFFE   +            0    3    1    0  read_data_from_sram7
   -      1     -    A    08       DFFE   +            0    3    1    0  read_data_from_sram8
   -      5     -    A    15       DFFE   +            0    3    1    0  read_data_from_sram9
   -      4     -    A    15       DFFE   +            0    3    1    0  read_data_from_sram10
   -      1     -    A    15       DFFE   +            0    3    1    0  read_data_from_sram11
   -      4     -    A    18       DFFE   +            0    3    1    0  read_data_from_sram12
   -      6     -    A    20       DFFE   +            0    3    1    0  read_data_from_sram13
   -      1     -    A    20       DFFE   +            0    3    1    0  read_data_from_sram14
   -      1     -    A    21       DFFE   +            0    3    1    0  read_data_from_sram15
   -      2     -    A    06       DFFE   +            0    3    1    0  read_data_from_sram16
   -      2     -    A    10       DFFE   +            0    3    1    0  read_data_from_sram17
   -      1     -    A    02       DFFE   +            0    3    1    0  read_data_from_sram18
   -      7     -    A    03       DFFE   +            0    3    1    0  read_data_from_sram19
   -      8     -    A    10       DFFE   +            0    3    1    0  read_data_from_sram20
   -      1     -    A    10       DFFE   +            0    3    1    0  read_data_from_sram21
   -      4     -    A    03       DFFE   +            0    3    1    0  read_data_from_sram22
   -      7     -    A    10       DFFE   +            0    3    1    0  read_data_from_sram23
   -      7     -    A    20       DFFE   +            0    3    1    0  read_data_from_sram24
   -      1     -    A    01       DFFE   +            0    3    1    0  read_data_from_sram25
   -      5     -    A    23       DFFE   +            0    3    1    0  read_data_from_sram26
   -      8     -    A    01       DFFE   +            0    3    1    0  read_data_from_sram27
   -      7     -    A    23       DFFE   +            0    3    1    0  read_data_from_sram28
   -      6     -    A    23       DFFE   +            0    3    1    0  read_data_from_sram29
   -      8     -    A    20       DFFE   +            0    3    1    0  read_data_from_sram30
   -      3     -    A    01       DFFE   +            0    3    1    0  read_data_from_sram31
   -      4     -    A    12      LCELL    s           1    0    1    0  req~1
   -      3     -    D    22       DFFE   +    !       0    3    1    0  /select~
   -      7     -    D    20       DFFE   +    !       2    1    1    2  /wr~
   -      3     -    A    13       DFFE   +            0    4    1    0  :113
   -      1     -    F    02       DFFE                0    2    1    0  :114
   -      1     -    D    20       DFFE   +            2    2    1    0  :115
   -      8     -    D    22        OR2    s           0    4    0    6  ~277~4~1
   -      1     -    D    07        OR2    s           0    2    0    1  ~277~4~2
   -      5     -    D    20        OR2    s           0    4    0    1  ~422~1
   -      6     -    D    20        OR2    s           1    3    0    1  ~433~1
   -      6     -    F    15        OR2    s           0    3    0    1  ~529~1
   -      2     -    E    04        OR2    s           0    3    0    1  ~529~2
   -      6     -    F    05        OR2    s           0    4    0    1  ~529~3
   -      8     -    F    17        OR2    s           0    4    0    1  ~529~4
   -      2     -    F    17        OR2    s           0    4    0    1  ~529~5
   -      5     -    F    02        OR2    s           0    4    0    1  ~529~6
   -      2     -    F    05        OR2    s           0    4    0    1  ~529~7
   -      4     -    F    09        OR2    s           0    4    0    1  ~529~8
   -      3     -    F    11        OR2    s           0    4    0    1  ~529~9
   -      6     -    F    02        OR2    s           0    4    0    1  ~529~10
   -      8     -    F    02        OR2                0    4    0    1  :529
   -      3     -    A    24        OR2        !       1    2    0    2  :604
   -      2     -    A    24        OR2        !       1    2    0    1  :608
   -      5     -    A    16       AND2                0    2    0    9  :630
   -      7     -    A    01       AND2                0    2    0    1  :685
   -      3     -    A    03       AND2                0    2    0    1  :687
   -      5     -    A    03       AND2                0    2    0    1  :689
   -      1     -    A    16       AND2                1    2    0    1  :735
   -      3     -    A    16       AND2                0    2    0   10  :739
   -      4     -    A    01       AND2                0    2    0    1  :759
   -      2     -    A    15       AND2                0    2    0    1  :761
   -      1     -    A    18       AND2                0    2    0    1  :765
   -      2     -    A    20       AND2                0    2    0    1  :769
   -      4     -    A    17       AND2                1    2    0    1  :876
   -      3     -    A    10       AND2                0    2    0   10  :880
   -      3     -    A    02       AND2                0    2    0    1  :965
   -      5     -    A    01       AND2                0    2    0    1  :967
   -      6     -    A    03       AND2                0    2    0    1  :973
   -      8     -    A    17       AND2                1    2    0    1  :1049
   -      2     -    A    17       AND2                0    2    0   11  :1053
   -      7     -    A    16       AND2    s           0    4    0    1  ~1054~1
   -      4     -    A    13       AND2    s   !       0    4    0    2  ~1054~2
   -      8     -    A    13        OR2    s           0    3    0    1  ~1054~3
   -      3     -    A    20       AND2                0    2    0    1  :1151
   -      8     -    A    23       AND2                0    2    0    1  :1155
   -      6     -    A    16        OR2    s           0    4    0    8  ~1202~1
   -      1     -    A    17        OR2    s           0    4    0    9  ~1218~1
   -      3     -    A    17        OR2    s           0    4    0    9  ~1234~1
   -      4     -    A    23        OR2    s           0    3    0   13  ~1240~1
   -      2     -    A    23        OR2    s           0    3    0    9  ~1250~1
   -      1     -    A    24        OR2    s           1    3    0    1  ~1253~1
   -      4     -    A    24        OR2    s           1    3    0    1  ~1253~2
   -      6     -    A    13        OR2    s           0    3    0    1  ~1253~3
   -      5     -    A    13       AND2    s           0    4    0    1  ~1253~4
   -      6     -    A    24       AND2                0    4    0    5  :1253
   -      8     -    A    24        OR2    s           1    3    0    1  ~1281~1
   -      7     -    D    07        OR2        !       1    2    0   10  :1283
   -      6     -    D    22        OR2                0    4    0    7  :1289


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register


Device-Specific Information:      e:\pci_sm_card\epld\work\10144-ok\fifowr.rpt
fifowr

** FASTTRACK INTERCONNECT UTILIZATION **

Row FastTrack Interconnect:

          Global         Left Half-      Right Half-
         FastTrack       FastTrack       FastTrack 
Row     Interconnect    Interconnect    Interconnect    Input Pins     Output Pins     Bidir Pins
A:      26/ 96( 27%)     5/ 48( 10%)    24/ 48( 50%)    1/16(  6%)      3/16( 18%)     1/16(  6%)
B:       4/ 96(  4%)     1/ 48(  2%)     3/ 48(  6%)    2/16( 12%)      3/16( 18%)     1/16(  6%)
C:       4/ 96(  4%)     2/ 48(  4%)     1/ 48(  2%)    0/16(  0%)      2/16( 12%)     3/16( 18%)
D:      10/ 96( 10%)     1/ 48(  2%)     7/ 48( 14%)    0/16(  0%)      6/16( 37%)     2/16( 12%)
E:      20/ 96( 20%)     5/ 48( 10%)     2/ 48(  4%)    0/16(  0%)      0/16(  0%)     8/16( 50%)
F:      29/ 96( 30%)    14/ 48( 29%)     7/ 48( 14%)    0/16(  0%)      2/16( 12%)     6/16( 37%)


Column FastTrack Interconnect:

         FastTrack                                 
Column  Interconnect    Input Pins     Output Pins     Bidir Pins
01:      7/24( 29%)     0/4(  0%)      1/4( 25%)       2/4( 50%)
02:      6/24( 25%)     0/4(  0%)      0/4(  0%)       1/4( 25%)
03:      4/24( 16%)     0/4(  0%)      1/4( 25%)       1/4( 25%)
04:      6/24( 25%)     0/4(  0%)      0/4(  0%)       2/4( 50%)
05:      3/24( 12%)     0/4(  0%)      1/4( 25%)       1/4( 25%)
06:      5/24( 20%)     0/4(  0%)      1/4( 25%)       1/4( 25%)
07:      3/24( 12%)     0/4(  0%)      2/4( 50%)       0/4(  0%)
08:      5/24( 20%)     0/4(  0%)      1/4( 25%)       1/4( 25%)
09:      4/24( 16%)     0/4(  0%)      2/4( 50%)       0/4(  0%)
10:      4/24( 16%)     0/4(  0%)      1/4( 25%)       1/4( 25%)
11:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
12:      3/24( 12%)     0/4(  0%)      2/4( 50%)       0/4(  0%)
13:      1/24(  4%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
14:      3/24( 12%)     0/4(  0%)      2/4( 50%)       0/4(  0%)
15:      5/24( 20%)     0/4(  0%)      1/4( 25%)       1/4( 25%)
16:      6/24( 25%)     0/4(  0%)      1/4( 25%)       2/4( 50%)
17:      3/24( 12%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
18:      5/24( 20%)     0/4(  0%)      1/4( 25%)       1/4( 25%)
19:      9/24( 37%)     0/4(  0%)      1/4( 25%)       1/4( 25%)
20:      7/24( 29%)     1/4( 25%)      0/4(  0%)       2/4( 50%)
21:      2/24(  8%)     0/4(  0%)      1/4( 25%)       1/4( 25%)
22:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
23:      6/24( 25%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
24:      5/24( 20%)     0/4(  0%)      0/4(  0%)       1/4( 25%)

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