📄 fifowr.rpt
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Total dedicated input pins used: 3/6 ( 50%)
Total I/O pins used: 83/96 ( 86%)
Total logic cells used: 161/1152 ( 13%)
Total embedded cells used: 0/48 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 2.88/4 ( 72%)
Total fan-in: 465/4608 ( 10%)
Total input pins required: 7
Total input I/O cell registers required: 0
Total output pins required: 39
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 40
Total reserved pins required 0
Total logic cells required: 161
Total flipflops required: 107
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 29/1152 ( 2%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 8 4 7 0 0 4 0 1 0 5 0 1 0 8 0 4 8 8 2 0 6 1 0 8 8 83/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 2/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
D: 0 0 0 0 0 0 7 0 0 0 0 0 0 1 0 0 0 0 1 0 7 0 8 0 0 24/0
E: 0 0 0 6 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 15/0
F: 0 8 0 0 8 0 0 0 6 0 4 0 0 0 0 3 0 8 0 0 0 0 0 0 0 37/0
Total: 8 12 7 6 8 4 7 5 6 5 4 1 0 9 2 7 8 16 3 0 13 1 8 13 8 161/0
Device-Specific Information: e:\pci_sm_card\epld\work\10144-ok\fifowr.rpt
fifowr
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
55 - - - -- INPUT G 0 0 0 1 bpclk
109 - - A -- BIDIR 0 1 0 2 dq0
110 - - - 01 BIDIR 0 1 0 2 dq1
111 - - - 01 BIDIR 0 1 0 2 dq2
112 - - - 02 BIDIR 0 1 0 2 dq3
113 - - - 03 BIDIR 0 1 0 2 dq4
114 - - - 04 BIDIR 0 1 0 2 dq5
117 - - - 05 BIDIR 0 1 0 2 dq6
118 - - - 06 BIDIR 0 1 0 2 dq7
120 - - - 08 BIDIR 0 1 0 1 dq8
130 - - - 15 BIDIR 0 1 0 1 dq9
131 - - - 16 BIDIR 0 1 0 1 dq10
132 - - - 16 BIDIR 0 1 0 1 dq11
133 - - - 18 BIDIR 0 1 0 1 dq12
135 - - - 19 BIDIR 0 1 0 1 dq13
136 - - - 20 BIDIR 0 1 0 1 dq14
138 - - - 21 BIDIR 0 1 0 1 dq15
30 - - F -- BIDIR 0 1 0 1 dq16
27 - - E -- BIDIR 0 1 0 1 dq17
26 - - E -- BIDIR 0 1 0 1 dq18
23 - - D -- BIDIR 0 1 0 1 dq19
91 - - C -- BIDIR 0 1 0 1 dq20
99 - - B -- BIDIR 0 1 0 1 dq21
116 - - - 04 BIDIR 0 1 0 1 dq22
121 - - - 10 BIDIR 0 1 0 1 dq23
137 - - - 20 BIDIR 0 1 0 1 dq24
17 - - D -- BIDIR 0 1 0 1 dq25
28 - - E -- BIDIR 0 1 0 1 dq26
29 - - E -- BIDIR 0 1 0 1 dq27
36 - - - 24 BIDIR 0 1 0 1 dq28
33 - - F -- BIDIR 0 1 0 1 dq29
32 - - F -- BIDIR 0 1 0 1 dq30
31 - - F -- BIDIR 0 1 0 1 dq31
56 - - - -- INPUT 0 0 0 7 /ptatn
96 - - B -- INPUT 0 0 0 0 /ptburst
97 - - B -- INPUT 0 0 0 4 ptwr
54 - - - -- INPUT G 0 0 0 0 /sysrst
90 - - C -- BIDIR 0 1 0 4 trans_data0
89 - - C -- BIDIR 0 1 0 4 trans_data1
87 - - E -- BIDIR 0 1 0 4 trans_data2
86 - - E -- BIDIR 0 1 0 4 trans_data3
83 - - E -- BIDIR 0 1 0 4 trans_data4
82 - - E -- BIDIR 0 1 0 4 trans_data5
81 - - F -- BIDIR 0 1 0 4 trans_data6
80 - - F -- BIDIR 0 1 0 4 trans_data7
41 - - - 20 INPUT 0 0 0 10 valid
101 - - A -- INPUT 0 0 0 4 wrfull
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\pci_sm_card\epld\work\10144-ok\fifowr.rpt
fifowr
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
10 - - B -- OUTPUT 0 1 0 0 adr2
12 - - C -- OUTPUT 0 1 0 0 adr3
13 - - C -- OUTPUT 0 0 0 0 adr4
18 - - D -- OUTPUT 0 1 0 0 adr5
79 - - F -- OUTPUT 0 0 0 0 adr6
119 - - - 07 OUTPUT 0 1 0 0 /be0
19 - - D -- OUTPUT 0 1 0 0 /be1
20 - - D -- OUTPUT 0 1 0 0 /be2
21 - - D -- OUTPUT 0 1 0 0 /be3
39 - - - 21 OUTPUT 0 0 0 0 CESHI
46 - - - 17 OUTPUT 0 1 0 0 clkout
109 - - A -- TRI 0 1 0 2 dq0
110 - - - 01 TRI 0 1 0 2 dq1
111 - - - 01 TRI 0 1 0 2 dq2
112 - - - 02 TRI 0 1 0 2 dq3
113 - - - 03 TRI 0 1 0 2 dq4
114 - - - 04 TRI 0 1 0 2 dq5
117 - - - 05 TRI 0 1 0 2 dq6
118 - - - 06 TRI 0 1 0 2 dq7
120 - - - 08 TRI 0 1 0 1 dq8
130 - - - 15 TRI 0 1 0 1 dq9
131 - - - 16 TRI 0 1 0 1 dq10
132 - - - 16 TRI 0 1 0 1 dq11
133 - - - 18 TRI 0 1 0 1 dq12
135 - - - 19 TRI 0 1 0 1 dq13
136 - - - 20 TRI 0 1 0 1 dq14
138 - - - 21 TRI 0 1 0 1 dq15
30 - - F -- TRI 0 1 0 1 dq16
27 - - E -- TRI 0 1 0 1 dq17
26 - - E -- TRI 0 1 0 1 dq18
23 - - D -- TRI 0 1 0 1 dq19
91 - - C -- TRI 0 1 0 1 dq20
99 - - B -- TRI 0 1 0 1 dq21
116 - - - 04 TRI 0 1 0 1 dq22
121 - - - 10 TRI 0 1 0 1 dq23
137 - - - 20 TRI 0 1 0 1 dq24
17 - - D -- TRI 0 1 0 1 dq25
28 - - E -- TRI 0 1 0 1 dq26
29 - - E -- TRI 0 1 0 1 dq27
36 - - - 24 TRI 0 1 0 1 dq28
33 - - F -- TRI 0 1 0 1 dq29
32 - - F -- TRI 0 1 0 1 dq30
31 - - F -- TRI 0 1 0 1 dq31
22 - - D -- OUTPUT 0 0 0 0 mode
42 - - - 19 OUTPUT 0 1 0 0 nvsram_wr
73 - - - 01 OUTPUT 0 1 0 0 nvsram_write_oe
98 - - B -- OUTPUT 0 1 0 0 /ptadr
37 - - - 23 OUTPUT 0 1 0 0 /ptrdy
9 - - B -- OUTPUT 0 1 0 0 /rd
100 - - A -- OUTPUT 0 0 0 0 rdfifo
88 - - D -- OUTPUT 0 1 0 0 req
140 - - - 22 OUTPUT 0 1 0 0 /select
90 - - C -- TRI 0 1 0 4 trans_data0
89 - - C -- TRI 0 1 0 4 trans_data1
87 - - E -- TRI 0 1 0 4 trans_data2
86 - - E -- TRI 0 1 0 4 trans_data3
83 - - E -- TRI 0 1 0 4 trans_data4
82 - - E -- TRI 0 1 0 4 trans_data5
81 - - F -- TRI 0 1 0 4 trans_data6
80 - - F -- TRI 0 1 0 4 trans_data7
8 - - A -- OUTPUT 0 1 0 0 /wr
102 - - A -- OUTPUT 0 1 0 0 wrfifo
78 - - F -- OUTPUT 0 1 0 0 write_addr0
72 - - - 03 OUTPUT 0 1 0 0 write_addr1
70 - - - 05 OUTPUT 0 1 0 0 write_addr2
69 - - - 06 OUTPUT 0 1 0 0 write_addr3
68 - - - 07 OUTPUT 0 1 0 0 write_addr4
67 - - - 08 OUTPUT 0 1 0 0 write_addr5
65 - - - 09 OUTPUT 0 1 0 0 write_addr6
64 - - - 09 OUTPUT 0 1 0 0 write_addr7
63 - - - 10 OUTPUT 0 1 0 0 write_addr8
62 - - - 11 OUTPUT 0 1 0 0 write_addr9
60 - - - 12 OUTPUT 0 1 0 0 write_addr10
59 - - - 12 OUTPUT 0 1 0 0 write_addr11
51 - - - 14 OUTPUT 0 1 0 0 write_addr12
49 - - - 14 OUTPUT 0 1 0 0 write_addr13
48 - - - 15 OUTPUT 0 1 0 0 write_addr14
47 - - - 16 OUTPUT 0 1 0 0 write_addr15
43 - - - 18 OUTPUT 0 1 0 0 write_addr16
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\pci_sm_card\epld\work\10144-ok\fifowr.rpt
fifowr
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
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