📄 fifowr.rpt
字号:
/ptadr~,
/ptrdy~,
/rd~,
/wr~,
fifo_oe
)
WITH STATES (
idle = B"00001000111111111",
addr = B"00000111000001110",
write = B"00000111000011010",
read = B"00000111000011100",
ready = B"00000111000010110",
turn = B"10001111111111110",
wait0 = B"01000111000010110",
wait1 = B"00101111111111110",
wait2 = B"00011111111111110"
);
asm_ctrl: MACHINE
OF BITS (
asm_ctrl~13,
asm_ctrl~12,
asm_ctrl~11,
asm_ctrl~10,
asm_ctrl~9,
asm_ctrl~8,
asm_ctrl~7,
asm_ctrl~6,
asm_ctrl~5,
asm_ctrl~4,
asm_ctrl~3,
asm_ctrl~2,
asm_ctrl~1
)
WITH STATES (
asm_idle = B"0000000000000",
asm_stuff = B"1100000000000",
asm_wait_one = B"1010000000000",
asm_wait_two = B"1001000000000",
asm_work_idle = B"1000100000000",
asm_work_byte0 = B"1000010000000",
asm_wait0 = B"1000001000000",
asm_work_byte1 = B"1000000100000",
asm_wait1 = B"1000000010000",
asm_work_byte2 = B"1000000001000",
asm_wait2 = B"1000000000100",
asm_work_byte3 = B"1000000000010",
asm_turn = B"1000000000001"
);
Device-Specific Information: e:\pci_sm_card\epld\work\10144-ok\fifowr.rpt
fifowr
***** Logic for device 'fifowr' compiled without errors.
Device: EPF10K20TC144-4
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
Device-Specific Information: e:\pci_sm_card\epld\work\10144-ok\fifowr.rpt
fifowr
** ERROR SUMMARY **
Info: Chip 'fifowr' in device 'EPF10K20TC144-4' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
R R R R R R
E E E E / E E
S S S S s S G G G G V S
E E E E e G V G E N N N N C E V
R R R R l N d d d d C d d d N R D D D D C R d / d C
V V V V e D q q q q C q q q d D V I I I I I V q d b d d q C d d d d d d
E E E E c I 1 2 1 1 I 1 1 1 q I E N N N N N E 2 q e q q 2 I q q q q q q
D D D D t O 5 4 4 3 O 2 1 0 9 O D T T T T T D 3 8 0 7 6 2 O 5 4 3 2 1 0
--------------------------------------------------------------------------_
/ 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 |_
/ 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 |
#TCK | 1 108 | ^DATA0
^CONF_DONE | 2 107 | ^DCLK
^nCEO | 3 106 | ^nCE
#TDO | 4 105 | #TDI
VCCIO | 5 104 | GNDIO
VCCINT | 6 103 | GNDINT
RESERVED | 7 102 | wrfifo
/wr | 8 101 | wrfull
/rd | 9 100 | rdfifo
adr2 | 10 99 | dq21
RESERVED | 11 98 | /ptadr
adr3 | 12 97 | ptwr
adr4 | 13 96 | /ptburst
RESERVED | 14 95 | RESERVED
GNDIO | 15 94 | VCCIO
GNDINT | 16 93 | VCCINT
dq25 | 17 92 | RESERVED
adr5 | 18 91 | dq20
/be1 | 19 EPF10K20TC144-4 90 | trans_data0
/be2 | 20 89 | trans_data1
/be3 | 21 88 | req
mode | 22 87 | trans_data2
dq19 | 23 86 | trans_data3
VCCIO | 24 85 | GNDIO
VCCINT | 25 84 | GNDINT
dq18 | 26 83 | trans_data4
dq17 | 27 82 | trans_data5
dq26 | 28 81 | trans_data6
dq27 | 29 80 | trans_data7
dq16 | 30 79 | adr6
dq31 | 31 78 | write_addr0
dq30 | 32 77 | ^MSEL0
dq29 | 33 76 | ^MSEL1
#TMS | 34 75 | VCCINT
^nSTATUS | 35 74 | ^nCONFIG
dq28 | 36 73 | nvsram_write_oe
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
/ R C G v n w R V c w w w G w V V / b / G G w w V w w w w G w w w w V w
p E E N a v r E C l r r r N r C C s p p N N r r C r r r r N r r r r C r
t S S D l s i S C k i i i D i C C y c t D D i i C i i i i D i i i i C i
r E H I i r t E I o t t t I t I I s l a I I t t I t t t t I t t t t I t
d R I O d a e R O u e e e O e N N r k t N N e e O e e e e O e e e e O e
y V m _ V t _ _ _ _ T T s n T T _ _ _ _ _ _ _ _ _ _ _
E _ a E a a a a t a a a a a a a a a a a
D w d D d d d d d d d d d d d d d d d
r d d d d d d d d d d d d d d d d
r r r r r r r r r r r r r r r r
1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1
6 5 4 3 2 1 0
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: e:\pci_sm_card\epld\work\10144-ok\fifowr.rpt
fifowr
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A1 8/ 8(100%) 4/ 8( 50%) 3/ 8( 37%) 1/2 0/2 10/22( 45%)
A2 4/ 8( 50%) 3/ 8( 37%) 0/ 8( 0%) 1/2 0/2 7/22( 31%)
A3 7/ 8( 87%) 4/ 8( 50%) 0/ 8( 0%) 1/2 0/2 9/22( 40%)
A6 4/ 8( 50%) 4/ 8( 50%) 1/ 8( 12%) 1/2 0/2 7/22( 31%)
A8 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 3/22( 13%)
A10 5/ 8( 62%) 4/ 8( 50%) 1/ 8( 12%) 1/2 0/2 7/22( 31%)
A12 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%)
A13 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 2/2 0/2 11/22( 50%)
A15 4/ 8( 50%) 3/ 8( 37%) 0/ 8( 0%) 1/2 0/2 6/22( 27%)
A16 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 7/22( 31%)
A17 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 0/2 6/22( 27%)
A18 2/ 8( 25%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 4/22( 18%)
A20 6/ 8( 75%) 4/ 8( 50%) 0/ 8( 0%) 1/2 0/2 8/22( 36%)
A21 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 3/22( 13%)
A23 8/ 8(100%) 3/ 8( 37%) 4/ 8( 50%) 1/2 0/2 8/22( 36%)
A24 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 7/22( 31%)
B14 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 1/2 0/2 3/22( 13%)
D7 7/ 8( 87%) 4/ 8( 50%) 4/ 8( 50%) 1/2 1/2 3/22( 13%)
D13 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 1/2 1/22( 4%)
D18 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%)
D20 7/ 8( 87%) 5/ 8( 62%) 0/ 8( 0%) 1/2 1/2 6/22( 27%)
D22 8/ 8(100%) 1/ 8( 12%) 6/ 8( 75%) 1/2 1/2 4/22( 18%)
E4 6/ 8( 75%) 3/ 8( 37%) 0/ 8( 0%) 1/2 0/2 6/22( 27%)
E8 4/ 8( 50%) 4/ 8( 50%) 2/ 8( 25%) 1/2 0/2 4/22( 18%)
E23 5/ 8( 62%) 5/ 8( 62%) 2/ 8( 25%) 1/2 1/2 5/22( 22%)
F2 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 2/2 0/2 12/22( 54%)
F5 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 1/2 0/2 9/22( 40%)
F9 6/ 8( 75%) 5/ 8( 62%) 3/ 8( 37%) 1/2 0/2 6/22( 27%)
F11 4/ 8( 50%) 3/ 8( 37%) 1/ 8( 12%) 1/2 0/2 5/22( 22%)
F15 3/ 8( 37%) 2/ 8( 25%) 1/ 8( 12%) 1/2 0/2 4/22( 18%)
F17 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 9/22( 40%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
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