📄 datasample.rpt
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NDFV = !O_E;
-- Node name is 'O_E' from file "datasample.tdf" line 17, column 3
-- Equation name is 'O_E', location is LC2_C9, type is buried.
O_E = DFFE(!O_E, GLOBAL( SH), VCC, VCC, VCC);
-- Node name is 'O_E~1' from file "datasample.tdf" line 17, column 3
-- Equation name is 'O_E~1', location is LC1_C3, type is buried.
-- synthesized logic cell
_LC1_C3 = LCELL( _IOC_122);
-- Node name is 'PCLK' from file "datasample.tdf" line 17, column 8
-- Equation name is 'PCLK', type is output
PCLK = _LC1_B6;
-- Node name is 'RAM_WR' from file "datasample.tdf" line 24, column 2
-- Equation name is 'RAM_WR', type is output
RAM_WR = GND;
-- Node name is 'RAM_WR_ADDR0' from file "datasample.tdf" line 19, column 13
-- Equation name is 'RAM_WR_ADDR0', type is output
RAM_WR_ADDR0 = _LC2_A5;
-- Node name is 'RAM_WR_ADDR1' from file "datasample.tdf" line 19, column 13
-- Equation name is 'RAM_WR_ADDR1', type is output
RAM_WR_ADDR1 = _LC6_A1;
-- Node name is 'RAM_WR_ADDR2' from file "datasample.tdf" line 19, column 13
-- Equation name is 'RAM_WR_ADDR2', type is output
RAM_WR_ADDR2 = _LC8_A1;
-- Node name is 'RAM_WR_ADDR3' from file "datasample.tdf" line 19, column 13
-- Equation name is 'RAM_WR_ADDR3', type is output
RAM_WR_ADDR3 = _LC7_A1;
-- Node name is 'RAM_WR_ADDR4' from file "datasample.tdf" line 19, column 13
-- Equation name is 'RAM_WR_ADDR4', type is output
RAM_WR_ADDR4 = _LC5_A1;
-- Node name is 'RAM_WR_ADDR5' from file "datasample.tdf" line 19, column 13
-- Equation name is 'RAM_WR_ADDR5', type is output
RAM_WR_ADDR5 = _LC3_A1;
-- Node name is 'RAM_WR_ADDR6' from file "datasample.tdf" line 19, column 13
-- Equation name is 'RAM_WR_ADDR6', type is output
RAM_WR_ADDR6 = _LC4_A1;
-- Node name is 'RAM_WR_ADDR7' from file "datasample.tdf" line 19, column 13
-- Equation name is 'RAM_WR_ADDR7', type is output
RAM_WR_ADDR7 = _LC5_A2;
-- Node name is 'RAM_WR_ADDR8' from file "datasample.tdf" line 19, column 13
-- Equation name is 'RAM_WR_ADDR8', type is output
RAM_WR_ADDR8 = _LC6_A2;
-- Node name is 'RAM_WR_ADDR9' from file "datasample.tdf" line 19, column 13
-- Equation name is 'RAM_WR_ADDR9', type is output
RAM_WR_ADDR9 = _LC7_A2;
-- Node name is 'RAM_WR_ADDR10' from file "datasample.tdf" line 19, column 13
-- Equation name is 'RAM_WR_ADDR10', type is output
RAM_WR_ADDR10 = _LC8_A2;
-- Node name is 'RAM_WR_ADDR11' from file "datasample.tdf" line 19, column 13
-- Equation name is 'RAM_WR_ADDR11', type is output
RAM_WR_ADDR11 = _LC1_A2;
-- Node name is 'RAM_WR_ADDR12' from file "datasample.tdf" line 19, column 13
-- Equation name is 'RAM_WR_ADDR12', type is output
RAM_WR_ADDR12 = _LC3_A2;
-- Node name is 'SYNC' from file "datasample.tdf" line 25, column 2
-- Equation name is 'SYNC', type is output
SYNC = _LC1_A4;
-- Node name is 'SYNC~1' from file "datasample.tdf" line 25, column 2
-- Equation name is 'SYNC~1', location is LC1_A4, type is buried.
-- synthesized logic cell
_LC1_A4 = LCELL( SH);
-- Node name is ':72' from file "datasample.tdf" line 19, column 13
-- Equation name is '_LC3_A2', type is buried
_LC3_A2 = DFFE( _EQ001, GLOBAL( SM_CLK), !SH, VCC, VCC);
_EQ001 = _LC3_A2 & !_LC8_A2
# !_LC2_A2 & _LC3_A2
# !_LC1_A2 & _LC3_A2
# _LC1_A2 & _LC2_A2 & !_LC3_A2 & _LC8_A2;
-- Node name is ':73' from file "datasample.tdf" line 19, column 13
-- Equation name is '_LC1_A2', type is buried
_LC1_A2 = DFFE( _EQ002, GLOBAL( SM_CLK), !SH, VCC, VCC);
_EQ002 = _LC1_A2 & !_LC8_A2
# _LC1_A2 & !_LC2_A2
# !_LC1_A2 & _LC2_A2 & _LC8_A2;
-- Node name is ':74' from file "datasample.tdf" line 19, column 13
-- Equation name is '_LC8_A2', type is buried
_LC8_A2 = DFFE( _EQ003, GLOBAL( SM_CLK), !SH, VCC, VCC);
_EQ003 = !_LC2_A2 & _LC8_A2
# _LC2_A2 & !_LC8_A2;
-- Node name is ':75' from file "datasample.tdf" line 19, column 13
-- Equation name is '_LC7_A2', type is buried
_LC7_A2 = DFFE( _EQ004, GLOBAL( SM_CLK), !SH, VCC, VCC);
_EQ004 = !_LC5_A2 & _LC7_A2
# !_LC1_A1 & _LC7_A2
# !_LC6_A2 & _LC7_A2
# _LC1_A1 & _LC5_A2 & _LC6_A2 & !_LC7_A2;
-- Node name is ':76' from file "datasample.tdf" line 19, column 13
-- Equation name is '_LC6_A2', type is buried
_LC6_A2 = DFFE( _EQ005, GLOBAL( SM_CLK), !SH, VCC, VCC);
_EQ005 = !_LC5_A2 & _LC6_A2
# !_LC1_A1 & _LC6_A2
# _LC1_A1 & _LC5_A2 & !_LC6_A2;
-- Node name is ':77' from file "datasample.tdf" line 19, column 13
-- Equation name is '_LC5_A2', type is buried
_LC5_A2 = DFFE( _EQ006, GLOBAL( SM_CLK), !SH, VCC, VCC);
_EQ006 = !_LC1_A1 & _LC5_A2
# _LC1_A1 & !_LC5_A2;
-- Node name is ':78' from file "datasample.tdf" line 19, column 13
-- Equation name is '_LC4_A1', type is buried
_LC4_A1 = DFFE( _EQ007, GLOBAL( SM_CLK), !SH, VCC, VCC);
_EQ007 = _LC4_A1 & !_LC5_A1
# !_LC2_A1 & _LC4_A1
# !_LC3_A1 & _LC4_A1
# _LC2_A1 & _LC3_A1 & !_LC4_A1 & _LC5_A1;
-- Node name is ':79' from file "datasample.tdf" line 19, column 13
-- Equation name is '_LC3_A1', type is buried
_LC3_A1 = DFFE( _EQ008, GLOBAL( SM_CLK), !SH, VCC, VCC);
_EQ008 = _LC3_A1 & !_LC5_A1
# !_LC2_A1 & _LC3_A1
# _LC2_A1 & !_LC3_A1 & _LC5_A1;
-- Node name is ':80' from file "datasample.tdf" line 19, column 13
-- Equation name is '_LC5_A1', type is buried
_LC5_A1 = DFFE( _EQ009, GLOBAL( SM_CLK), !SH, VCC, VCC);
_EQ009 = !_LC2_A1 & _LC5_A1
# _LC2_A1 & !_LC5_A1;
-- Node name is ':81' from file "datasample.tdf" line 19, column 13
-- Equation name is '_LC7_A1', type is buried
_LC7_A1 = DFFE( _EQ010, GLOBAL( SM_CLK), !SH, VCC, VCC);
_EQ010 = !_LC6_A1 & _LC7_A1
# !_LC2_A5 & _LC7_A1
# _LC7_A1 & !_LC8_A1
# _LC2_A5 & _LC6_A1 & !_LC7_A1 & _LC8_A1;
-- Node name is ':82' from file "datasample.tdf" line 19, column 13
-- Equation name is '_LC8_A1', type is buried
_LC8_A1 = DFFE( _EQ011, GLOBAL( SM_CLK), !SH, VCC, VCC);
_EQ011 = !_LC6_A1 & _LC8_A1
# !_LC2_A5 & _LC8_A1
# _LC2_A5 & _LC6_A1 & !_LC8_A1;
-- Node name is ':83' from file "datasample.tdf" line 19, column 13
-- Equation name is '_LC6_A1', type is buried
_LC6_A1 = DFFE( _EQ012, GLOBAL( SM_CLK), !SH, VCC, VCC);
_EQ012 = !_LC2_A5 & _LC6_A1
# _LC2_A5 & !_LC6_A1;
-- Node name is ':84' from file "datasample.tdf" line 19, column 13
-- Equation name is '_LC2_A5', type is buried
_LC2_A5 = DFFE(!_LC2_A5, GLOBAL( SM_CLK), !SH, VCC, VCC);
-- Node name is ':85' from file "datasample.tdf" line 17, column 8
-- Equation name is '_LC1_B6', type is buried
_LC1_B6 = DFFE( SM_CLK, GLOBAL( SRC_CLK), VCC, VCC, VCC);
-- Node name is ':101' from file "datasample.tdf" line 35, column 31
-- Equation name is '_LC2_A1', type is buried
_LC2_A1 = LCELL( _EQ013);
_EQ013 = _LC2_A5 & _LC6_A1 & _LC7_A1 & _LC8_A1;
-- Node name is ':113' from file "datasample.tdf" line 35, column 31
-- Equation name is '_LC1_A1', type is buried
_LC1_A1 = LCELL( _EQ014);
_EQ014 = _LC2_A1 & _LC3_A1 & _LC4_A1 & _LC5_A1;
-- Node name is ':125' from file "datasample.tdf" line 35, column 31
-- Equation name is '_LC2_A2', type is buried
_LC2_A2 = LCELL( _EQ015);
_EQ015 = _LC1_A1 & _LC5_A2 & _LC6_A2 & _LC7_A2;
Project Information e:\hanpj\pld\dma\10k208\datasample.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = on
Automatic Register Packing = on
Automatic Open-Drain Pins = on
Automatic Implement in EAB = on
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 13,674K
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