📄 datasample.rpt
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119 - - C -- OUTPUT 0 1 0 0 DATA_OUT4
31 - - B -- OUTPUT 0 1 0 0 DATA_OUT5
44 - - C -- OUTPUT 0 1 0 0 DATA_OUT6
133 - - B -- OUTPUT 0 1 0 0 DATA_OUT7
122 - - C -- FF +s 0 1 0 1 DFV
121 - - C -- OUTPUT 0 1 0 0 NDFV
168 - - - 06 OUTPUT 0 1 0 0 PCLK
10 - - A -- OUTPUT 0 0 0 0 RAM_WR
149 - - A -- OUTPUT 0 1 0 0 RAM_WR_ADDR0
17 - - A -- OUTPUT 0 1 0 0 RAM_WR_ADDR1
19 - - A -- OUTPUT 0 1 0 0 RAM_WR_ADDR2
18 - - A -- OUTPUT 0 1 0 0 RAM_WR_ADDR3
16 - - A -- OUTPUT 0 1 0 0 RAM_WR_ADDR4
148 - - A -- OUTPUT 0 1 0 0 RAM_WR_ADDR5
147 - - A -- OUTPUT 0 1 0 0 RAM_WR_ADDR6
144 - - A -- OUTPUT 0 1 0 0 RAM_WR_ADDR7
143 - - A -- OUTPUT 0 1 0 0 RAM_WR_ADDR8
142 - - A -- OUTPUT 0 1 0 0 RAM_WR_ADDR9
141 - - A -- OUTPUT 0 1 0 0 RAM_WR_ADDR10
11 - - A -- OUTPUT 0 1 0 0 RAM_WR_ADDR11
12 - - A -- OUTPUT 0 1 0 0 RAM_WR_ADDR12
150 - - A -- OUTPUT 0 1 0 0 SYNC
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\hanpj\pld\dma\10k208\datasample.rpt
datasample
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - B 13 LCELL s 1 0 1 0 DATA_OUT0~1
- 6 - B 14 LCELL s 1 0 1 0 DATA_OUT1~1
- 3 - C 16 LCELL s 1 0 1 0 DATA_OUT2~1
- 2 - B 07 LCELL s 1 0 1 0 DATA_OUT3~1
- 3 - C 10 LCELL s 1 0 1 0 DATA_OUT4~1
- 8 - B 15 LCELL s 1 0 1 0 DATA_OUT5~1
- 5 - C 17 LCELL s 1 0 1 0 DATA_OUT6~1
- 3 - B 08 LCELL s 1 0 1 0 DATA_OUT7~1
- 2 - C 09 DFFE + 0 0 1 0 O_E
- 1 - C 03 LCELL s 0 1 1 0 O_E~1
- 1 - A 04 LCELL s 1 0 1 0 SYNC~1
- 3 - A 02 DFFE + 1 3 1 0 :72
- 1 - A 02 DFFE + 1 2 1 1 :73
- 8 - A 02 DFFE + 1 1 1 2 :74
- 7 - A 02 DFFE + 1 3 1 1 :75
- 6 - A 02 DFFE + 1 2 1 2 :76
- 5 - A 02 DFFE + 1 1 1 3 :77
- 4 - A 01 DFFE + 1 3 1 1 :78
- 3 - A 01 DFFE + 1 2 1 2 :79
- 5 - A 01 DFFE + 1 1 1 3 :80
- 7 - A 01 DFFE + 1 3 1 1 :81
- 8 - A 01 DFFE + 1 2 1 2 :82
- 6 - A 01 DFFE + 1 1 1 3 :83
- 2 - A 05 DFFE + 1 0 1 4 :84
- 1 - B 06 DFFE + 1 0 1 0 :85
- 2 - A 01 AND2 0 4 0 4 :101
- 1 - A 01 AND2 0 4 0 4 :113
- 2 - A 02 AND2 0 4 0 3 :125
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\hanpj\pld\dma\10k208\datasample.rpt
datasample
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 7/ 96( 7%) 9/ 48( 18%) 0/ 48( 0%) 0/16( 0%) 15/16( 93%) 0/16( 0%)
B: 5/ 96( 5%) 2/ 48( 4%) 3/ 48( 6%) 5/16( 31%) 5/16( 31%) 0/16( 0%)
C: 4/ 96( 4%) 3/ 48( 6%) 2/ 48( 4%) 3/16( 18%) 5/16( 31%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\hanpj\pld\dma\10k208\datasample.rpt
datasample
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 16 SH
INPUT 14 SM_CLK
DFF 9 :85
INPUT 1 SRC_CLK
Device-Specific Information: e:\hanpj\pld\dma\10k208\datasample.rpt
datasample
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 16 SH
Device-Specific Information: e:\hanpj\pld\dma\10k208\datasample.rpt
datasample
** EQUATIONS **
SH : INPUT;
SM_CLK : INPUT;
SRC_CLK : INPUT;
-- Node name is ':71' from file "datasample.tdf" line 18, column 10
-- Equation name is '_IOC_24', type is buried
DATA_IN0 : INPUT;
_IOC_24 = DFFE(DATA_IN0, _LC1_B6, VCC, VCC, VCC);
-- Node name is ':70' from file "datasample.tdf" line 18, column 10
-- Equation name is '_IOC_28', type is buried
DATA_IN1 : INPUT;
_IOC_28 = DFFE(DATA_IN1, _LC1_B6, VCC, VCC, VCC);
-- Node name is ':69' from file "datasample.tdf" line 18, column 10
-- Equation name is '_IOC_40', type is buried
DATA_IN2 : INPUT;
_IOC_40 = DFFE(DATA_IN2, _LC1_B6, VCC, VCC, VCC);
-- Node name is ':68' from file "datasample.tdf" line 18, column 10
-- Equation name is '_IOC_26', type is buried
DATA_IN3 : INPUT;
_IOC_26 = DFFE(DATA_IN3, _LC1_B6, VCC, VCC, VCC);
-- Node name is ':67' from file "datasample.tdf" line 18, column 10
-- Equation name is '_IOC_39', type is buried
DATA_IN4 : INPUT;
_IOC_39 = DFFE(DATA_IN4, _LC1_B6, VCC, VCC, VCC);
-- Node name is ':66' from file "datasample.tdf" line 18, column 10
-- Equation name is '_IOC_27', type is buried
DATA_IN5 : INPUT;
_IOC_27 = DFFE(DATA_IN5, _LC1_B6, VCC, VCC, VCC);
-- Node name is ':65' from file "datasample.tdf" line 18, column 10
-- Equation name is '_IOC_38', type is buried
DATA_IN6 : INPUT;
_IOC_38 = DFFE(DATA_IN6, _LC1_B6, VCC, VCC, VCC);
-- Node name is ':64' from file "datasample.tdf" line 18, column 10
-- Equation name is '_IOC_25', type is buried
DATA_IN7 : INPUT;
_IOC_25 = DFFE(DATA_IN7, _LC1_B6, VCC, VCC, VCC);
-- Node name is 'DATA_OUT0~1' from file "datasample.tdf" line 18, column 10
-- Equation name is 'DATA_OUT0~1', location is LC6_B13, type is buried.
-- synthesized logic cell
_LC6_B13 = LCELL( _IOC_24);
-- Node name is 'DATA_OUT0' from file "datasample.tdf" line 18, column 10
-- Equation name is 'DATA_OUT0', type is output
DATA_OUT0 = _LC6_B13;
-- Node name is 'DATA_OUT1~1' from file "datasample.tdf" line 18, column 10
-- Equation name is 'DATA_OUT1~1', location is LC6_B14, type is buried.
-- synthesized logic cell
_LC6_B14 = LCELL( _IOC_28);
-- Node name is 'DATA_OUT1' from file "datasample.tdf" line 18, column 10
-- Equation name is 'DATA_OUT1', type is output
DATA_OUT1 = _LC6_B14;
-- Node name is 'DATA_OUT2~1' from file "datasample.tdf" line 18, column 10
-- Equation name is 'DATA_OUT2~1', location is LC3_C16, type is buried.
-- synthesized logic cell
_LC3_C16 = LCELL( _IOC_40);
-- Node name is 'DATA_OUT2' from file "datasample.tdf" line 18, column 10
-- Equation name is 'DATA_OUT2', type is output
DATA_OUT2 = _LC3_C16;
-- Node name is 'DATA_OUT3~1' from file "datasample.tdf" line 18, column 10
-- Equation name is 'DATA_OUT3~1', location is LC2_B7, type is buried.
-- synthesized logic cell
_LC2_B7 = LCELL( _IOC_26);
-- Node name is 'DATA_OUT3' from file "datasample.tdf" line 18, column 10
-- Equation name is 'DATA_OUT3', type is output
DATA_OUT3 = _LC2_B7;
-- Node name is 'DATA_OUT4~1' from file "datasample.tdf" line 18, column 10
-- Equation name is 'DATA_OUT4~1', location is LC3_C10, type is buried.
-- synthesized logic cell
_LC3_C10 = LCELL( _IOC_39);
-- Node name is 'DATA_OUT4' from file "datasample.tdf" line 18, column 10
-- Equation name is 'DATA_OUT4', type is output
DATA_OUT4 = _LC3_C10;
-- Node name is 'DATA_OUT5~1' from file "datasample.tdf" line 18, column 10
-- Equation name is 'DATA_OUT5~1', location is LC8_B15, type is buried.
-- synthesized logic cell
_LC8_B15 = LCELL( _IOC_27);
-- Node name is 'DATA_OUT5' from file "datasample.tdf" line 18, column 10
-- Equation name is 'DATA_OUT5', type is output
DATA_OUT5 = _LC8_B15;
-- Node name is 'DATA_OUT6~1' from file "datasample.tdf" line 18, column 10
-- Equation name is 'DATA_OUT6~1', location is LC5_C17, type is buried.
-- synthesized logic cell
_LC5_C17 = LCELL( _IOC_38);
-- Node name is 'DATA_OUT6' from file "datasample.tdf" line 18, column 10
-- Equation name is 'DATA_OUT6', type is output
DATA_OUT6 = _LC5_C17;
-- Node name is 'DATA_OUT7~1' from file "datasample.tdf" line 18, column 10
-- Equation name is 'DATA_OUT7~1', location is LC3_B8, type is buried.
-- synthesized logic cell
_LC3_B8 = LCELL( _IOC_25);
-- Node name is 'DATA_OUT7' from file "datasample.tdf" line 18, column 10
-- Equation name is 'DATA_OUT7', type is output
DATA_OUT7 = _LC3_B8;
-- Node name is 'DFV' = 'O_E~2' from file "datasample.tdf" line 17, column 3
-- Equation name is 'DFV', location is IOC_122, type is output.
DFV = _IOC_122;
-- Node name is 'O_E~2' from file "datasample.tdf" line 17, column 3
-- Equation name is '_IOC_122', location is IOC_122, type is buried.
_IOC_122 = DFFE(!_LC1_C3, GLOBAL( SH), VCC, VCC, VCC);
-- Node name is 'NDFV' from file "datasample.tdf" line 42, column 2
-- Equation name is 'NDFV', type is output
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