📄 datasample.rpt
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Project Information e:\hanpj\pld\dma\10k208\datasample.rpt
MAX+plus II Compiler Report File
Version 8.3 4/02/98
Compiled: 05/20/03 00:55:28
Copyright (C) 1988-1998 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
Untitled
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
datasample
EPF10K10QC208-3 11 26 0 0 0 % 28 4 %
User Pins: 11 26 0
Device-Specific Information: e:\hanpj\pld\dma\10k208\datasample.rpt
datasample
***** Logic for device 'datasample' compiled without errors.
Device: EPF10K10QC208-3
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R
E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E
S S S S S S S S S S S S S S S S S S S S G G G V S S S S S S S S S S S S S S S S S S S S
E E E E E E E G E E E E E E V E E E E E G E E N N N C E E V E E E E E E G E E E E V E E E E E E E E
R R R R R R R N R R R R R R C R R R R R N R R D D D C R R C R R R R R R N R R P R R C R R R R R R R R
V V V V V V V D V V V V V V C V V V V V D V V I I I I V V C V V V V V V D V V C V V C V V V V V V V V
E E E E E E E I E E E E E E I E E E E E I E E N N S N N E E I E E E E E E I E E L E E I E E E E E E E E
D D D D D D D O D D D D D D O D D D D D O D D T T H T T D D O D D D D D D O D D K D D O D D D D D D D D
----------------------------------------------------------------------------------------------------------_
/ 208 206 204 202 200 198 196 194 192 190 188 186 184 182 180 178 176 174 172 170 168 166 164 162 160 158 |_
/ 207 205 203 201 199 197 195 193 191 189 187 185 183 181 179 177 175 173 171 169 167 165 163 161 159 157 |
#TCK | 1 156 | ^DATA0
^CONF_DONE | 2 155 | ^DCLK
^nCEO | 3 154 | ^nCE
#TDO | 4 153 | #TDI
VCCIO | 5 152 | GNDIO
VCCINT | 6 151 | GNDINT
N.C. | 7 150 | SYNC
N.C. | 8 149 | RAM_WR_ADDR0
N.C. | 9 148 | RAM_WR_ADDR5
RAM_WR | 10 147 | RAM_WR_ADDR6
RAM_WR_ADDR11 | 11 146 | VCCIO
RAM_WR_ADDR12 | 12 145 | VCCINT
RESERVED | 13 144 | RAM_WR_ADDR7
N.C. | 14 143 | RAM_WR_ADDR8
N.C. | 15 142 | RAM_WR_ADDR9
RAM_WR_ADDR4 | 16 141 | RAM_WR_ADDR10
RAM_WR_ADDR1 | 17 140 | N.C.
RAM_WR_ADDR3 | 18 139 | N.C.
RAM_WR_ADDR2 | 19 138 | VCCIO
GNDIO | 20 137 | VCCINT
GNDINT | 21 136 | RESERVED
VCCIO | 22 135 | DATA_OUT3
VCCINT | 23 134 | RESERVED
DATA_IN0 | 24 133 | DATA_OUT7
DATA_IN7 | 25 132 | RESERVED
DATA_IN3 | 26 131 | RESERVED
DATA_IN5 | 27 EPF10K10QC208-3 130 | GNDIO
DATA_IN1 | 28 129 | GNDINT
DATA_OUT0 | 29 128 | RESERVED
DATA_OUT1 | 30 127 | RESERVED
DATA_OUT5 | 31 126 | N.C.
GNDIO | 32 125 | N.C.
GNDINT | 33 124 | GNDIO
VCCIO | 34 123 | GNDINT
VCCINT | 35 122 | DFV
N.C. | 36 121 | NDFV
N.C. | 37 120 | RESERVED
DATA_IN6 | 38 119 | DATA_OUT4
DATA_IN4 | 39 118 | VCCIO
DATA_IN2 | 40 117 | VCCINT
DATA_OUT2 | 41 116 | RESERVED
VCCIO | 42 115 | RESERVED
VCCINT | 43 114 | N.C.
DATA_OUT6 | 44 113 | N.C.
RESERVED | 45 112 | RESERVED
RESERVED | 46 111 | RESERVED
RESERVED | 47 110 | VCCIO
GNDIO | 48 109 | VCCINT
GNDINT | 49 108 | ^MSEL0
#TMS | 50 107 | ^MSEL1
#nTRST | 51 106 | VCCINT
^nSTATUS | 52 105 | ^nCONFIG
| 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 _|
\ 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 |
\-----------------------------------------------------------------------------------------------------------
R R R R R R G R R R R R R V R R R R R G R R R V V G S S G G R V R R R R R R G R R R R R R V R R R R R R
E E E E E E N E E E E E E C E E E E E N E E E C C N M R N N E C E E E E E E N E E E E E E C E E E E E E
S S S S S S D S S S S S S C S S S S S D S S S C C D _ C D D S C S S S S S S D S S S S S S C S S S S S S
E E E E E E I E E E E E E I E E E E E I E E E I I I C _ I I E I E E E E E E I E E E E E E I E E E E E E
R R R R R R O R R R R R R O R R R R R O R R R N N N L C N N R O R R R R R R O R R R R R R O R R R R R R
V V V V V V V V V V V V V V V V V V V V T T T K L T T V V V V V V V V V V V V V V V V V V V
E E E E E E E E E E E E E E E E E E E E K E E E E E E E E E E E E E E E E E E E
D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D
N.C. = Not Connected.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System-Programming or Configuration Pin. The JTAG inputs (TMS, TCK, TDI) should be tied to VCC when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: e:\hanpj\pld\dma\10k208\datasample.rpt
datasample
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A1 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 1/2 1/2 2/22( 9%)
A2 7/ 8( 87%) 0/ 8( 0%) 6/ 8( 75%) 1/2 1/2 2/22( 9%)
A4 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%)
A5 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 1/22( 4%)
B6 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 1/22( 4%)
B7 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%)
B8 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%)
B13 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%)
B14 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%)
B15 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%)
C3 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%)
C9 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 0/22( 0%)
C10 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%)
C16 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%)
C17 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 3/6 ( 50%)
Total I/O pins used: 34/128 ( 26%)
Total logic cells used: 28/576 ( 4%)
Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 2.17/4 ( 54%)
Total fan-in: 61/2304 ( 2%)
Total input pins required: 11
Total input I/O cell registers required: 8
Total output pins required: 26
Total output I/O cell registers required: 1
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 28
Total flipflops required: 15
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 11/ 576 ( 1%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 8 7 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17/0
B: 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 6/0
C: 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 5/0
Total: 8 7 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 28/0
Device-Specific Information: e:\hanpj\pld\dma\10k208\datasample.rpt
datasample
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
24 - - B -- FF 0 0 0 1 DATA_IN0
28 - - B -- FF 0 0 0 1 DATA_IN1
40 - - C -- FF 0 0 0 1 DATA_IN2
26 - - B -- FF 0 0 0 1 DATA_IN3
39 - - C -- FF 0 0 0 1 DATA_IN4
27 - - B -- FF 0 0 0 1 DATA_IN5
38 - - C -- FF 0 0 0 1 DATA_IN6
25 - - B -- FF 0 0 0 1 DATA_IN7
183 - - - -- INPUT 0 0 0 14 SH
79 - - - -- INPUT 0 0 0 1 SM_CLK
80 - - - -- INPUT 0 0 0 0 SRC_CLK
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\hanpj\pld\dma\10k208\datasample.rpt
datasample
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
29 - - B -- OUTPUT 0 1 0 0 DATA_OUT0
30 - - B -- OUTPUT 0 1 0 0 DATA_OUT1
41 - - C -- OUTPUT 0 1 0 0 DATA_OUT2
135 - - B -- OUTPUT 0 1 0 0 DATA_OUT3
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