📄 10k208.rpt
字号:
- 4 - C 19 DFFE 1 1 0 2 |dmard:19|start_read_id
- 3 - C 19 DFFE + 0 1 0 1 |dmard:19|start_read_id_reset
- 5 - C 13 DFFE + 1 1 0 3 |dmard:19|trans_control~1
- 2 - C 13 DFFE + 0 1 0 3 |dmard:19|trans_control~2
- 5 - C 24 DFFE + 0 4 0 3 |dmard:19|trans_control~3
- 4 - C 24 DFFE + 0 1 0 13 |dmard:19|trans_control~4
- 3 - C 13 DFFE + 1 2 0 31 |dmard:19|trans_control~5
- 1 - C 19 DFFE + 0 1 0 3 |dmard:19|trans_control~6
- 7 - C 19 DFFE + 1 3 0 3 |dmard:19|trans_control~7
- 2 - C 19 DFFE + 1 2 0 2 |dmard:19|trans_control~8
- 8 - C 13 DFFE + 0 3 0 1 |dmard:19|trans_data_dff0
- 6 - F 24 DFFE + 0 3 0 1 |dmard:19|trans_data_dff1
- 5 - F 24 DFFE + 0 3 0 1 |dmard:19|trans_data_dff2
- 8 - F 24 DFFE + 0 3 0 1 |dmard:19|trans_data_dff3
- 2 - B 23 DFFE + 0 3 0 1 |dmard:19|trans_data_dff4
- 4 - B 23 DFFE + 0 3 0 1 |dmard:19|trans_data_dff5
- 6 - B 23 DFFE + 0 3 0 1 |dmard:19|trans_data_dff6
- 3 - C 22 DFFE + 0 3 0 1 |dmard:19|trans_data_dff7
- 4 - C 13 DFFE + 0 1 1 0 |dmard:19|t2_data0
- 6 - A 20 DFFE + 0 1 1 0 |dmard:19|t2_data1
- 1 - F 24 DFFE + 0 1 1 0 |dmard:19|t2_data2
- 4 - F 24 DFFE + 0 1 1 0 |dmard:19|t2_data3
- 8 - B 18 DFFE + 0 1 1 0 |dmard:19|t2_data4
- 7 - B 23 DFFE + 0 1 1 0 |dmard:19|t2_data5
- 8 - B 23 DFFE + 0 1 1 0 |dmard:19|t2_data6
- 2 - C 22 DFFE + 0 1 1 0 |dmard:19|t2_data7
- 3 - C 24 DFFE + 0 1 1 0 |dmard:19|:63
- 5 - C 15 AND2 0 2 0 4 |dmard:19|:182
- 7 - B 05 AND2 0 2 0 1 |dmard:19|:186
- 1 - B 05 AND2 0 3 0 1 |dmard:19|:190
- 4 - B 05 AND2 0 4 0 4 |dmard:19|:194
- 6 - B 02 AND2 0 2 0 1 |dmard:19|:198
- 8 - B 02 AND2 0 3 0 1 |dmard:19|:202
- 1 - B 02 AND2 0 4 0 4 |dmard:19|:206
- 5 - C 06 AND2 0 2 0 1 |dmard:19|:210
- 6 - C 06 AND2 0 3 0 1 |dmard:19|:214
- 8 - C 06 AND2 0 4 0 4 |dmard:19|:218
- 5 - C 01 AND2 0 2 0 1 |dmard:19|:222
- 6 - C 01 AND2 0 3 0 1 |dmard:19|:226
- 2 - C 01 AND2 0 4 0 1 |dmard:19|:230
- 4 - C 15 AND2 0 2 0 4 |dmard:19|:256
- 2 - C 15 AND2 0 2 0 1 |dmard:19|:260
- 4 - C 18 AND2 0 3 0 1 |dmard:19|:264
- 1 - C 18 AND2 0 4 0 2 |dmard:19|:268
- 2 - C 18 AND2 0 2 0 2 |dmard:19|:272
- 3 - C 14 AND2 0 2 0 4 |dmard:19|:276
- 4 - C 14 AND2 0 2 0 1 |dmard:19|:280
- 7 - C 14 AND2 0 3 0 1 |dmard:19|:284
- 2 - C 14 AND2 0 4 0 4 |dmard:19|:288
- 3 - C 17 AND2 0 2 0 1 |dmard:19|:292
- 6 - C 17 AND2 0 3 0 1 |dmard:19|:296
- 7 - C 17 AND2 0 4 0 1 |dmard:19|:300
- 5 - C 18 AND2 ! 0 4 0 1 |dmard:19|:408
- 1 - C 14 OR2 s 0 3 0 1 |dmard:19|~415~1
- 4 - C 17 OR2 ! 0 4 0 2 |dmard:19|:417
- 1 - C 24 OR2 ! 0 4 0 1 |dmard:19|:422
- 5 - C 19 AND2 s 0 4 0 1 |dmard:19|~587~1
- 1 - C 13 OR2 s 0 4 0 29 |dmard:19|~619~1
- 6 - C 13 AND2 s ! 0 4 0 9 |dmard:19|~661~1
- 6 - C 19 OR2 s 1 3 0 1 |dmard:19|~677~1
- 2 - D 18 DFFE + 0 0 0 6 |nvsram:3|rd_address0
- 5 - D 16 DFFE + 0 2 0 5 |nvsram:3|rd_address1
- 6 - D 16 DFFE + 0 3 0 4 |nvsram:3|rd_address2
- 3 - D 16 DFFE + 0 3 0 3 |nvsram:3|rd_address3
- 4 - D 13 DFFE + 0 2 0 5 |nvsram:3|rd_address4
- 5 - D 13 DFFE + 0 3 0 4 |nvsram:3|rd_address5
- 2 - D 13 DFFE + 0 3 0 3 |nvsram:3|rd_address6
- 6 - D 19 DFFE + 0 2 0 5 |nvsram:3|rd_address7
- 5 - D 19 DFFE + 0 3 0 4 |nvsram:3|rd_address8
- 3 - D 19 DFFE + 0 3 0 3 |nvsram:3|rd_address9
- 3 - D 08 DFFE + 0 2 0 5 |nvsram:3|rd_address10
- 8 - D 08 DFFE + 0 3 0 4 |nvsram:3|rd_address11
- 4 - D 08 DFFE + 0 3 0 3 |nvsram:3|rd_address12
- 3 - F 11 DFFE + 0 2 0 4 |nvsram:3|rd_address13
- 5 - F 11 DFFE + 0 3 0 3 |nvsram:3|rd_address14
- 7 - F 11 DFFE + 0 2 0 3 |nvsram:3|rd_address15
- 2 - F 11 DFFE + 0 3 0 2 |nvsram:3|rd_address16
- 1 - A 19 LCELL s 0 1 1 0 |nvsram:3|temp_data0~1
- 1 - A 17 LCELL s 0 1 1 0 |nvsram:3|temp_data1~1
- 2 - B 17 LCELL s 0 1 1 0 |nvsram:3|temp_data2~1
- 1 - E 04 LCELL s 0 1 1 0 |nvsram:3|temp_data3~1
- 1 - B 04 LCELL s 0 1 1 0 |nvsram:3|temp_data4~1
- 8 - B 06 LCELL s 0 1 1 0 |nvsram:3|temp_data5~1
- 1 - D 06 LCELL s 0 1 1 0 |nvsram:3|temp_data6~1
- 2 - C 05 LCELL s 0 1 1 0 |nvsram:3|temp_data7~1
- 5 - D 08 OR2 s 0 3 0 1 |nvsram:3|~148~1
- 8 - D 13 OR2 s 0 3 0 1 |nvsram:3|~148~2
- 1 - D 19 OR2 s 0 4 0 1 |nvsram:3|~148~3
- 8 - F 11 OR2 s 0 4 0 1 |nvsram:3|~148~4
- 4 - D 19 OR2 s 0 4 0 1 |nvsram:3|~148~5
- 2 - D 08 OR2 0 4 0 16 |nvsram:3|:148
- 7 - D 16 AND2 0 2 0 1 |nvsram:3|:155
- 2 - D 16 AND2 0 4 0 4 |nvsram:3|:163
- 7 - D 13 AND2 0 2 0 1 |nvsram:3|:167
- 1 - D 13 AND2 0 4 0 4 |nvsram:3|:175
- 7 - D 19 AND2 0 2 0 1 |nvsram:3|:179
- 8 - D 19 AND2 0 4 0 4 |nvsram:3|:187
- 7 - D 08 AND2 0 2 0 1 |nvsram:3|:191
- 1 - D 08 AND2 0 4 0 3 |nvsram:3|:199
- 4 - F 11 AND2 0 3 0 2 |nvsram:3|:207
- 1 - D 18 OR2 2 1 1 0 |nvsram:3|:252
- 4 - D 16 OR2 2 1 1 0 |nvsram:3|:255
- 1 - D 16 OR2 2 1 1 0 |nvsram:3|:258
- 8 - D 16 OR2 2 1 1 0 |nvsram:3|:261
- 3 - D 13 OR2 2 1 1 0 |nvsram:3|:264
- 6 - D 13 OR2 2 1 1 0 |nvsram:3|:267
- 1 - D 20 OR2 2 1 1 0 |nvsram:3|:270
- 2 - D 19 OR2 2 1 1 0 |nvsram:3|:273
- 2 - E 09 OR2 2 1 1 0 |nvsram:3|:276
- 2 - E 10 OR2 2 1 1 0 |nvsram:3|:279
- 6 - D 08 OR2 2 1 1 0 |nvsram:3|:282
- 4 - D 10 OR2 2 1 1 0 |nvsram:3|:285
- 1 - E 21 OR2 2 1 1 0 |nvsram:3|:288
- 1 - F 11 OR2 2 1 1 0 |nvsram:3|:291
- 4 - F 22 OR2 2 1 1 0 |nvsram:3|:294
- 6 - F 11 OR2 2 1 1 0 |nvsram:3|:297
- 4 - F 21 OR2 2 1 1 0 |nvsram:3|:300
- 6 - C 10 OR2 0 3 1 0 |pingp:4|:186
- 3 - C 08 OR2 0 3 1 0 |pingp:4|:189
- 5 - B 05 OR2 0 3 1 0 |pingp:4|:192
- 8 - B 05 OR2 0 3 1 0 |pingp:4|:195
- 5 - B 03 OR2 0 3 1 0 |pingp:4|:198
- 5 - B 02 OR2 0 3 1 0 |pingp:4|:201
- 6 - B 01 OR2 0 3 1 0 |pingp:4|:204
- 2 - B 03 OR2 0 3 1 0 |pingp:4|:207
- 6 - B 03 OR2 0 3 1 0 |pingp:4|:210
- 4 - C 06 OR2 0 3 1 0 |pingp:4|:213
- 8 - C 08 OR2 0 3 1 0 |pingp:4|:216
- 2 - C 08 OR2 0 3 1 0 |pingp:4|:219
- 8 - C 10 OR2 0 3 1 0 |pingp:4|:222
- 3 - C 10 OR2 0 3 1 0 |pingp:4|:225
- 3 - C 11 OR2 0 3 1 0 |pingp:4|:228
- 5 - B 21 OR2 s 0 2 1 0 |pingp:4|~230~1
- 8 - B 01 OR2 0 2 1 0 |pingp:4|:230
- 1 - C 10 OR2 0 3 1 0 |pingp:4|:233
- 1 - C 07 OR2 0 3 1 0 |pingp:4|:236
- 6 - B 05 OR2 0 3 1 0 |pingp:4|:239
- 4 - B 11 OR2 0 3 1 0 |pingp:4|:242
- 1 - B 03 OR2 0 3 1 0 |pingp:4|:245
- 3 - B 02 OR2 0 3 1 0 |pingp:4|:248
- 5 - B 01 OR2 0 3 1 0 |pingp:4|:251
- 7 - B 01 OR2 0 3 1 0 |pingp:4|:254
- 2 - C 06 OR2 0 3 1 0 |pingp:4|:257
- 8 - C 12 OR2 0 3 1 0 |pingp:4|:260
- 6 - C 08 OR2 0 3 1 0 |pingp:4|:263
- 4 - C 08 OR2 0 3 1 0 |pingp:4|:266
- 2 - C 10 OR2 0 3 1 0 |pingp:4|:269
- 5 - C 10 OR2 0 3 1 0 |pingp:4|:272
- 7 - C 11 OR2 0 3 1 0 |pingp:4|:275
- 6 - B 21 OR2 0 2 1 0 |pingp:4|:279
- 7 - C 13 OR2 0 3 0 1 |pingp:4|:282
- 2 - F 24 OR2 0 3 0 1 |pingp:4|:285
- 3 - F 24 OR2 0 3 0 1 |pingp:4|:288
- 7 - F 24 OR2 0 3 0 1 |pingp:4|:291
- 1 - B 23 OR2 0 3 0 1 |pingp:4|:294
- 3 - B 23 OR2 0 3 0 1 |pingp:4|:297
- 5 - B 23 OR2 0 3 0 1 |pingp:4|:300
- 1 - C 22 OR2 0 3 0 1 |pingp:4|:303
- 8 - F 23 LCELL s 1 0 1 0 rclk~1
- 2 - B 08 LCELL s 1 0 1 0 TM_OE/~1
- 6 - E 11 LCELL s 1 0 1 0 TM_WE/~1
- 2 - B 22 LCELL s 1 0 1 0 208C~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\pci_sm_card\epld\work\10k208\10k208.rpt
10k208
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
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