📄 10k208.rpt
字号:
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
88 - - - 09 OUTPUT 0 1 0 0 RAMA_ADDR0
93 - - - 07 OUTPUT 0 1 0 0 RAMA_ADDR1
95 - - - 06 OUTPUT 0 1 0 0 RAMA_ADDR2
97 - - - 05 OUTPUT 0 1 0 0 RAMA_ADDR3
100 - - - 04 OUTPUT 0 1 0 0 RAMA_ADDR4
104 - - - 01 OUTPUT 0 1 0 0 RAMA_ADDR5
103 - - - 02 OUTPUT 0 1 0 0 RAMA_ADDR6
101 - - - 03 OUTPUT 0 1 0 0 RAMA_ADDR7
99 - - - 04 OUTPUT 0 1 0 0 RAMA_ADDR8
96 - - - 05 OUTPUT 0 1 0 0 RAMA_ADDR9
94 - - - 07 OUTPUT 0 1 0 0 RAMA_ADDR10
92 - - - 08 OUTPUT 0 1 0 0 RAMA_ADDR11
89 - - - 09 OUTPUT 0 1 0 0 RAMA_ADDR12
87 - - - 10 OUTPUT 0 1 0 0 RAMA_ADDR13
85 - - - 11 OUTPUT 0 1 0 0 RAMA_ADDR14
75 - - - 13 TRI 0 1 0 1 RAMA_DATA0
73 - - - 14 TRI 0 1 0 1 RAMA_DATA1
70 - - - 15 TRI 0 1 0 1 RAMA_DATA2
69 - - - 15 TRI 0 1 0 1 RAMA_DATA3
71 - - - 14 TRI 0 1 0 1 RAMA_DATA4
74 - - - 13 TRI 0 1 0 1 RAMA_DATA5
83 - - - 12 TRI 0 1 0 1 RAMA_DATA6
86 - - - 11 TRI 0 1 0 1 RAMA_DATA7
90 - - - 08 OUTPUT 0 1 0 0 RAMA_OE
102 - - - 02 OUTPUT 0 1 0 0 RAMA_WR
157 - - A -- OUTPUT 0 1 0 0 RAMB_ADDR0
128 - - D -- OUTPUT 0 1 0 0 RAMB_ADDR1
132 - - C -- OUTPUT 0 1 0 0 RAMB_ADDR2
134 - - C -- OUTPUT 0 1 0 0 RAMB_ADDR3
136 - - C -- OUTPUT 0 1 0 0 RAMB_ADDR4
142 - - B -- OUTPUT 0 1 0 0 RAMB_ADDR5
141 - - B -- OUTPUT 0 1 0 0 RAMB_ADDR6
139 - - B -- OUTPUT 0 1 0 0 RAMB_ADDR7
135 - - C -- OUTPUT 0 1 0 0 RAMB_ADDR8
133 - - C -- OUTPUT 0 1 0 0 RAMB_ADDR9
131 - - C -- OUTPUT 0 1 0 0 RAMB_ADDR10
127 - - D -- OUTPUT 0 1 0 0 RAMB_ADDR11
125 - - E -- OUTPUT 0 1 0 0 RAMB_ADDR12
122 - - E -- OUTPUT 0 1 0 0 RAMB_ADDR13
120 - - E -- OUTPUT 0 1 0 0 RAMB_ADDR14
116 - - F -- TRI 0 1 0 1 RAMB_DATA0
114 - - F -- TRI 0 1 0 1 RAMB_DATA1
112 - - F -- TRI 0 1 0 1 RAMB_DATA2
111 - - F -- TRI 0 1 0 1 RAMB_DATA3
113 - - F -- TRI 0 1 0 1 RAMB_DATA4
115 - - F -- TRI 0 1 0 1 RAMB_DATA5
119 - - E -- TRI 0 1 0 1 RAMB_DATA6
121 - - E -- TRI 0 1 0 1 RAMB_DATA7
126 - - D -- OUTPUT 0 1 0 0 RAMB_OE
140 - - B -- OUTPUT 0 1 0 0 RAMB_WR
205 - - - 24 OUTPUT 0 1 0 0 rclk
193 - - - 17 OUTPUT 0 1 0 0 TMA0
192 - - - 16 OUTPUT 0 1 0 0 TMA1
191 - - - 16 OUTPUT 0 1 0 0 TMA2
190 - - - 15 OUTPUT 0 1 0 0 TMA3
189 - - - 14 OUTPUT 0 1 0 0 TMA4
187 - - - 14 OUTPUT 0 1 0 0 TMA5
198 - - - 20 OUTPUT 0 1 0 0 TMA6
199 - - - 20 OUTPUT 0 1 0 0 TMA7
175 - - - 10 OUTPUT 0 1 0 0 TMA8
174 - - - 09 OUTPUT 0 1 0 0 TMA9
170 - - - 07 OUTPUT 0 1 0 0 TMA10
173 - - - 09 OUTPUT 0 1 0 0 TMA11
200 - - - 21 OUTPUT 0 1 0 0 TMA12
176 - - - 11 OUTPUT 0 1 0 0 TMA13
202 - - - 21 OUTPUT 0 1 0 0 TMA14
179 - - - 12 OUTPUT 0 1 0 0 TMA15
203 - - - 22 OUTPUT 0 1 0 0 TMA16
197 - - - 19 TRI 0 1 0 0 TMD0
196 - - - 18 TRI 0 1 0 0 TMD1
195 - - - 18 TRI 0 1 0 0 TMD2
164 - - - 04 TRI 0 1 0 0 TMD3
166 - - - 04 TRI 0 1 0 0 TMD4
167 - - - 05 TRI 0 1 0 0 TMD5
168 - - - 06 TRI 0 1 0 0 TMD6
169 - - - 06 TRI 0 1 0 0 TMD7
172 - - - 08 OUTPUT 0 1 0 0 TM_OE/
177 - - - 11 OUTPUT 0 1 0 0 TM_WE/
8 - - A -- TRI 0 1 0 1 TRANS_DATA0
9 - - A -- TRI 0 1 0 1 TRANS_DATA1
11 - - B -- TRI 0 1 0 1 TRANS_DATA2
12 - - B -- TRI 0 1 0 1 TRANS_DATA3
13 - - B -- TRI 0 1 0 1 TRANS_DATA4
14 - - B -- TRI 0 1 0 1 TRANS_DATA5
15 - - B -- TRI 0 1 0 1 TRANS_DATA6
17 - - C -- TRI 0 1 0 1 TRANS_DATA7
55 - - - 24 OUTPUT 0 1 0 0 VALID
57 - - - 22 OUTPUT 0 1 0 0 208B
58 - - - 21 OUTPUT 0 1 0 0 208C
56 - - - 23 OUTPUT 0 1 0 0 208D
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\pci_sm_card\epld\work\10k208\10k208.rpt
10k208
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 4 - F 14 DFFE s 1 1 1 0 |datasample:2|data0~1
- 1 - F 14 DFFE 1 1 1 0 |datasample:2|data0
- 8 - F 13 DFFE s 1 1 1 0 |datasample:2|data1~1
- 4 - F 13 DFFE 1 1 1 0 |datasample:2|data1
- 8 - A 15 DFFE s 1 1 1 0 |datasample:2|data2~1
- 6 - A 15 DFFE 1 1 1 0 |datasample:2|data2
- 1 - A 15 DFFE s 1 1 1 0 |datasample:2|data3~1
- 7 - A 15 DFFE 1 1 1 0 |datasample:2|data3
- 2 - F 14 DFFE s 1 1 1 0 |datasample:2|data4~1
- 5 - F 14 DFFE 1 1 1 0 |datasample:2|data4
- 5 - F 13 DFFE s 1 1 1 0 |datasample:2|data5~1
- 3 - F 13 DFFE 1 1 1 0 |datasample:2|data5
- 1 - E 12 DFFE s 1 1 1 0 |datasample:2|data6~1
- 8 - E 12 DFFE 1 1 1 0 |datasample:2|data6
- 4 - E 12 DFFE s 1 1 1 0 |datasample:2|data7~1
- 6 - E 12 DFFE 1 1 1 0 |datasample:2|data7
- 1 - C 08 DFFE 1 0 1 41 |datasample:2|o_e
- 7 - D 07 DFFE s 1 0 1 0 |datasample:2|o_e~1
- 1 - A 23 DFFE s 1 0 1 0 |datasample:2|o_e~2
- 4 - C 12 DFFE 1 4 0 2 |datasample:2|:65
- 3 - C 12 DFFE 1 3 0 3 |datasample:2|:66
- 6 - C 12 DFFE 1 2 0 4 |datasample:2|:67
- 2 - C 12 DFFE 1 4 0 3 |datasample:2|:68
- 5 - C 12 DFFE 1 3 0 4 |datasample:2|:69
- 1 - C 12 DFFE 1 2 0 5 |datasample:2|:70
- 1 - B 01 DFFE 1 4 0 3 |datasample:2|:71
- 3 - B 01 DFFE 1 3 0 4 |datasample:2|:72
- 2 - B 01 DFFE 1 2 0 5 |datasample:2|:73
- 5 - B 09 DFFE 1 4 0 3 |datasample:2|:74
- 2 - B 09 DFFE 1 3 0 4 |datasample:2|:75
- 3 - B 09 DFFE 1 2 0 5 |datasample:2|:76
- 6 - B 09 DFFE 1 3 0 3 |datasample:2|:77
- 4 - B 09 DFFE 1 2 0 4 |datasample:2|:78
- 8 - B 09 DFFE 1 1 0 5 |datasample:2|:79
- 1 - B 22 DFFE + 1 0 0 34 |datasample:2|:80
- 7 - B 09 AND2 0 3 0 4 |datasample:2|:101
- 1 - B 09 AND2 0 4 0 4 |datasample:2|:113
- 4 - B 01 AND2 0 4 0 4 |datasample:2|:125
- 7 - C 12 AND2 0 4 0 3 |datasample:2|:137
- 8 - C 15 DFFE + 0 2 0 2 |dmard:19|count0
- 7 - C 15 DFFE + 0 3 0 1 |dmard:19|count1
- 1 - C 15 DFFE + 0 3 0 3 |dmard:19|count2
- 7 - C 18 DFFE + 0 3 0 3 |dmard:19|count3
- 6 - C 18 DFFE + 0 3 0 2 |dmard:19|count4
- 8 - C 18 DFFE + 0 3 0 2 |dmard:19|count5
- 3 - C 18 DFFE + 0 3 0 2 |dmard:19|count6
- 6 - C 14 DFFE + 0 3 0 4 |dmard:19|count7
- 5 - C 14 DFFE + 0 3 0 3 |dmard:19|count8
- 8 - C 14 DFFE + 0 3 0 2 |dmard:19|count9
- 1 - C 17 DFFE + 0 3 0 4 |dmard:19|count10
- 5 - C 17 DFFE + 0 3 0 3 |dmard:19|count11
- 2 - C 17 DFFE + 0 3 0 3 |dmard:19|count12
- 2 - C 24 DFFE + 0 3 0 2 |dmard:19|count13
- 6 - C 15 DFFE + 0 2 0 4 |dmard:19|rd_addr0
- 3 - C 15 DFFE + 0 3 0 3 |dmard:19|rd_addr1
- 3 - B 05 DFFE + 0 3 0 5 |dmard:19|rd_addr2
- 2 - B 05 DFFE + 0 3 0 4 |dmard:19|rd_addr3
- 8 - B 03 DFFE + 0 3 0 3 |dmard:19|rd_addr4
- 4 - B 02 DFFE + 0 3 0 5 |dmard:19|rd_addr5
- 7 - B 02 DFFE + 0 3 0 4 |dmard:19|rd_addr6
- 2 - B 02 DFFE + 0 3 0 3 |dmard:19|rd_addr7
- 3 - C 06 DFFE + 0 3 0 5 |dmard:19|rd_addr8
- 7 - C 06 DFFE + 0 3 0 4 |dmard:19|rd_addr9
- 1 - C 06 DFFE + 0 3 0 3 |dmard:19|rd_addr10
- 4 - C 01 DFFE + 0 3 0 5 |dmard:19|rd_addr11
- 3 - C 01 DFFE + 0 3 0 4 |dmard:19|rd_addr12
- 1 - C 01 DFFE + 0 3 0 3 |dmard:19|rd_addr13
- 1 - C 11 DFFE + 0 3 0 2 |dmard:19|rd_addr14
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