📄 10k208.rpt
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B1 8/ 8(100%) 4/ 8( 50%) 4/ 8( 50%) 1/2 1/2 6/22( 27%)
B2 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 1/2 0/2 5/22( 22%)
B3 5/ 8( 62%) 4/ 8( 50%) 1/ 8( 12%) 1/2 0/2 9/22( 40%)
B4 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%)
B5 8/ 8(100%) 3/ 8( 37%) 3/ 8( 37%) 1/2 0/2 7/22( 31%)
B6 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%)
B8 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%)
B9 8/ 8(100%) 2/ 8( 25%) 5/ 8( 62%) 1/2 1/2 2/22( 9%)
B11 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
B17 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%)
B18 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
B21 2/ 8( 25%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
B22 2/ 8( 25%) 2/ 8( 25%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
B23 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 9/22( 40%)
C1 6/ 8( 75%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 3/22( 13%)
C5 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%)
C6 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 1/2 0/2 6/22( 27%)
C7 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
C8 6/ 8( 75%) 5/ 8( 62%) 2/ 8( 25%) 1/2 0/2 7/22( 31%)
C10 6/ 8( 75%) 6/ 8( 75%) 0/ 8( 0%) 0/2 0/2 7/22( 31%)
C11 3/ 8( 37%) 2/ 8( 25%) 0/ 8( 0%) 1/2 0/2 5/22( 22%)
C12 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 1/2 1/2 5/22( 22%)
C13 8/ 8(100%) 4/ 8( 50%) 3/ 8( 37%) 1/2 0/2 7/22( 31%)
C14 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 4/22( 18%)
C15 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 1/2 0/2 2/22( 9%)
C17 7/ 8( 87%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 5/22( 22%)
C18 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 5/22( 22%)
C19 7/ 8( 87%) 0/ 8( 0%) 1/ 8( 12%) 2/2 1/2 6/22( 27%)
C22 3/ 8( 37%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 5/22( 22%)
C24 5/ 8( 62%) 2/ 8( 25%) 3/ 8( 37%) 1/2 0/2 5/22( 22%)
D6 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%)
D7 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
D8 8/ 8(100%) 4/ 8( 50%) 3/ 8( 37%) 1/2 1/2 9/22( 40%)
D10 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
D13 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 1/2 1/2 5/22( 22%)
D16 8/ 8(100%) 3/ 8( 37%) 4/ 8( 50%) 1/2 1/2 6/22( 27%)
D18 2/ 8( 25%) 1/ 8( 12%) 1/ 8( 12%) 1/2 1/2 2/22( 9%)
D19 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 1/2 1/2 8/22( 36%)
D20 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
E4 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%)
E9 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
E10 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
E11 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%)
E12 4/ 8( 50%) 4/ 8( 50%) 2/ 8( 25%) 1/2 0/2 3/22( 13%)
E21 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
F11 8/ 8(100%) 4/ 8( 50%) 2/ 8( 25%) 1/2 1/2 6/22( 27%)
F13 4/ 8( 50%) 3/ 8( 37%) 2/ 8( 25%) 1/2 0/2 3/22( 13%)
F14 4/ 8( 50%) 4/ 8( 50%) 2/ 8( 25%) 1/2 0/2 3/22( 13%)
F21 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
F22 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
F23 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%)
F24 8/ 8(100%) 3/ 8( 37%) 0/ 8( 0%) 1/2 0/2 9/22( 40%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 5/6 ( 83%)
Total I/O pins used: 117/141 ( 82%)
Total logic cells used: 230/1152 ( 19%)
Total embedded cells used: 0/48 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 2.81/4 ( 70%)
Total fan-in: 647/4608 ( 14%)
Total input pins required: 32
Total input I/O cell registers required: 0
Total output pins required: 66
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 24
Total reserved pins required 0
Total logic cells required: 230
Total flipflops required: 108
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 33/1152 ( 2%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 1 0 1 1 0 0 1 0 8/0
B: 8 8 5 1 8 1 0 1 8 0 1 0 0 0 0 0 0 1 1 0 0 2 2 8 0 55/0
C: 6 0 0 0 1 8 1 6 0 6 3 8 0 8 8 8 0 7 8 7 0 0 3 0 5 93/0
D: 0 0 0 0 0 1 1 8 0 1 0 0 0 8 0 0 8 0 2 8 1 0 0 0 0 38/0
E: 0 0 0 1 0 0 0 0 1 1 1 4 0 0 0 0 0 0 0 0 0 1 0 0 0 9/0
F: 0 0 0 0 0 0 0 0 0 0 8 0 0 4 4 0 0 0 0 0 0 1 1 1 8 27/0
Total: 14 8 5 2 9 10 2 15 9 8 13 12 0 20 12 12 8 9 11 16 2 4 6 10 13 230/0
Device-Specific Information: e:\pci_sm_card\epld\work\10k208\10k208.rpt
10k208
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
79 - - - -- INPUT G 0 0 0 0 BPCLK
143 - - B -- INPUT 0 0 0 2 DATA_IN0
144 - - B -- INPUT 0 0 0 2 DATA_IN1
147 - - A -- INPUT 0 0 0 2 DATA_IN2
148 - - A -- INPUT 0 0 0 2 DATA_IN3
149 - - A -- INPUT 0 0 0 2 DATA_IN4
150 - - A -- INPUT 0 0 0 2 DATA_IN5
163 - - - 03 INPUT 0 0 0 2 DATA_IN6
162 - - - 03 INPUT 0 0 0 2 DATA_IN7
182 - - - -- INPUT G 0 0 0 20 NVSRAM_WRITE_OE
75 - - - 13 BIDIR 0 1 0 1 RAMA_DATA0
73 - - - 14 BIDIR 0 1 0 1 RAMA_DATA1
70 - - - 15 BIDIR 0 1 0 1 RAMA_DATA2
69 - - - 15 BIDIR 0 1 0 1 RAMA_DATA3
71 - - - 14 BIDIR 0 1 0 1 RAMA_DATA4
74 - - - 13 BIDIR 0 1 0 1 RAMA_DATA5
83 - - - 12 BIDIR 0 1 0 1 RAMA_DATA6
86 - - - 11 BIDIR 0 1 0 1 RAMA_DATA7
116 - - F -- BIDIR 0 1 0 1 RAMB_DATA0
114 - - F -- BIDIR 0 1 0 1 RAMB_DATA1
112 - - F -- BIDIR 0 1 0 1 RAMB_DATA2
111 - - F -- BIDIR 0 1 0 1 RAMB_DATA3
113 - - F -- BIDIR 0 1 0 1 RAMB_DATA4
115 - - F -- BIDIR 0 1 0 1 RAMB_DATA5
119 - - E -- BIDIR 0 1 0 1 RAMB_DATA6
121 - - E -- BIDIR 0 1 0 1 RAMB_DATA7
7 - - A -- INPUT 0 0 0 19 SH
184 - - - -- INPUT 0 0 0 2 SM_CLK
183 - - - -- INPUT G 0 0 0 1 SRC_CLK
54 - - - 24 INPUT 0 0 0 1 TM_WR/
8 - - A -- BIDIR 0 1 0 1 TRANS_DATA0
9 - - A -- BIDIR 0 1 0 1 TRANS_DATA1
11 - - B -- BIDIR 0 1 0 1 TRANS_DATA2
12 - - B -- BIDIR 0 1 0 1 TRANS_DATA3
13 - - B -- BIDIR 0 1 0 1 TRANS_DATA4
14 - - B -- BIDIR 0 1 0 1 TRANS_DATA5
15 - - B -- BIDIR 0 1 0 1 TRANS_DATA6
17 - - C -- BIDIR 0 1 0 1 TRANS_DATA7
25 - - D -- INPUT 0 0 0 1 WR_ADDR0
26 - - D -- INPUT 0 0 0 1 WR_ADDR1
27 - - D -- INPUT 0 0 0 1 WR_ADDR2
28 - - D -- INPUT 0 0 0 1 WR_ADDR3
29 - - D -- INPUT 0 0 0 1 WR_ADDR4
30 - - D -- INPUT 0 0 0 1 WR_ADDR5
31 - - D -- INPUT 0 0 0 1 WR_ADDR6
36 - - E -- INPUT 0 0 0 1 WR_ADDR7
37 - - E -- INPUT 0 0 0 1 WR_ADDR8
38 - - E -- INPUT 0 0 0 1 WR_ADDR9
39 - - E -- INPUT 0 0 0 1 WR_ADDR10
40 - - E -- INPUT 0 0 0 1 WR_ADDR11
41 - - E -- INPUT 0 0 0 1 WR_ADDR12
44 - - F -- INPUT 0 0 0 1 WR_ADDR13
45 - - F -- INPUT 0 0 0 1 WR_ADDR14
46 - - F -- INPUT 0 0 0 1 WR_ADDR15
53 - - F -- INPUT 0 0 0 1 WR_ADDR16
78 - - - -- INPUT 0 0 0 3 WRFULL
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\pci_sm_card\epld\work\10k208\10k208.rpt
10k208
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