📄 10k208.rpt
字号:
|dmard:19|trans_control~8,
|dmard:19|trans_control~7,
|dmard:19|trans_control~6,
|dmard:19|trans_control~5,
|dmard:19|trans_control~4,
|dmard:19|trans_control~3,
|dmard:19|trans_control~2,
|dmard:19|trans_control~1
)
WITH STATES (
asm_idle = B"00000000",
t_idle = B"11000000",
t_start = B"10100000",
t_read = B"10010000",
t_wait_one = B"10001000",
t_wait_two = B"10000100",
t_wait_three = B"10000010",
t_wait_four = B"10000001"
);
Project Information e:\pci_sm_card\epld\work\10k208\10k208.rpt
** FILE HIERARCHY **
|datasample:2|
|nvsram:3|
|pingp:4|
|dmard:19|
Device-Specific Information: e:\pci_sm_card\epld\work\10k208\10k208.rpt
10k208
***** Logic for device '10k208' compiled without errors.
Device: EPF10K20RC208-4
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
Device-Specific Information: e:\pci_sm_card\epld\work\10k208\10k208.rpt
10k208
** ERROR SUMMARY **
Info: Chip '10k208' in device 'EPF10K20RC208-4' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
N
V
S
R
A
M R
_ A
R R R R R W R D D R R R R M
E E E E E S R E A A E E E E B
S S S S S G S R I V S T T T T S S S S _
E E E E T T G T V G E N M C T C E T V M T T M G T V A A E E E E A
R R R r R M M N M T T T T T C T T T T T N T R D _ _ E C R M C _ M T T M _ N M T T T T C T _ _ R R R R D
V V V c V A A D A M M M M M C M M M M M D M V I C C _ I V A C W A M M A O D A M M M M C M I I V V V V D
E E E l E 1 1 I 1 A A D D D I A A A A A I A E N L L O N E 1 I E 1 A A 1 E I 1 D D D D I D N N E E E E R
D D D k D 6 4 O 2 7 6 0 1 2 O 0 1 2 3 4 O 5 D T K K E T D 5 O / 3 8 9 1 / O 0 7 6 5 4 O 3 6 7 D D D D 0
----------------------------------------------------------------------------------------------------------_
/ 208 206 204 202 200 198 196 194 192 190 188 186 184 182 180 178 176 174 172 170 168 166 164 162 160 158 |_
/ 207 205 203 201 199 197 195 193 191 189 187 185 183 181 179 177 175 173 171 169 167 165 163 161 159 157 |
#TCK | 1 156 | ^DATA0
^CONF_DONE | 2 155 | ^DCLK
^nCEO | 3 154 | ^nCE
#TDO | 4 153 | #TDI
VCCIO | 5 152 | GNDIO
VCCINT | 6 151 | GNDINT
SH | 7 150 | DATA_IN5
TRANS_DATA0 | 8 149 | DATA_IN4
TRANS_DATA1 | 9 148 | DATA_IN3
RESERVED | 10 147 | DATA_IN2
TRANS_DATA2 | 11 146 | VCCIO
TRANS_DATA3 | 12 145 | VCCINT
TRANS_DATA4 | 13 144 | DATA_IN1
TRANS_DATA5 | 14 143 | DATA_IN0
TRANS_DATA6 | 15 142 | RAMB_ADDR5
RESERVED | 16 141 | RAMB_ADDR6
TRANS_DATA7 | 17 140 | RAMB_WR
RESERVED | 18 139 | RAMB_ADDR7
RESERVED | 19 138 | VCCIO
GNDIO | 20 137 | VCCINT
GNDINT | 21 136 | RAMB_ADDR4
VCCIO | 22 135 | RAMB_ADDR8
VCCINT | 23 134 | RAMB_ADDR3
RESERVED | 24 133 | RAMB_ADDR9
WR_ADDR0 | 25 132 | RAMB_ADDR2
WR_ADDR1 | 26 131 | RAMB_ADDR10
WR_ADDR2 | 27 EPF10K20RC208-4 130 | GNDIO
WR_ADDR3 | 28 129 | GNDINT
WR_ADDR4 | 29 128 | RAMB_ADDR1
WR_ADDR5 | 30 127 | RAMB_ADDR11
WR_ADDR6 | 31 126 | RAMB_OE
GNDIO | 32 125 | RAMB_ADDR12
GNDINT | 33 124 | GNDIO
VCCIO | 34 123 | GNDINT
VCCINT | 35 122 | RAMB_ADDR13
WR_ADDR7 | 36 121 | RAMB_DATA7
WR_ADDR8 | 37 120 | RAMB_ADDR14
WR_ADDR9 | 38 119 | RAMB_DATA6
WR_ADDR10 | 39 118 | VCCIO
WR_ADDR11 | 40 117 | VCCINT
WR_ADDR12 | 41 116 | RAMB_DATA0
VCCIO | 42 115 | RAMB_DATA5
VCCINT | 43 114 | RAMB_DATA1
WR_ADDR13 | 44 113 | RAMB_DATA4
WR_ADDR14 | 45 112 | RAMB_DATA2
WR_ADDR15 | 46 111 | RAMB_DATA3
RESERVED | 47 110 | VCCIO
GNDIO | 48 109 | VCCINT
GNDINT | 49 108 | ^MSEL0
#TMS | 50 107 | ^MSEL1
#TRST | 51 106 | VCCINT
^nSTATUS | 52 105 | ^nCONFIG
| 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 _|
\ 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 |
\-----------------------------------------------------------------------------------------------------------
W T V 2 2 2 G R R R R R R V R R R R R G R R R V V W B G G G R V R R R R R R G R R R R R R V R R R R R R
R M A 0 0 0 N E E E E E E C E E A A A N A A A C C R P N N N A C A A A A A A N A A A A A A C A A A A A A
_ _ L 8 8 8 D S S S S S S C S S M M M D M M M C C F C D D D M C M M M M M M D M M M M M M C M M M M M M
A W I D B C I E E E E E E I E E A A A I A A A I I U L I I I A I A A A A A A I A A A A A A I A A A A A A
D R D O R R R R R R O R R _ _ _ O _ _ _ N N L K N N N _ O _ _ _ _ _ _ O _ _ _ _ _ _ O _ _ _ _ _ _
D / V V V V V V V V D D D D D D T T L T T T D A D A A A O A A A A A A A A A W A A
R E E E E E E E E A A A A A A A D A D D D E D D D D D D D D D R D D
1 D D D D D D D D T T T T T T T D T D D D D D D D D D D D D D D
6 A A A A A A A R A R R R R R R R R R R R R R R
3 2 4 1 5 0 6 1 7 1 0 1 1 1 1 2 9 3 8 4 7 6 5
4 3 2 1 0
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: e:\pci_sm_card\epld\work\10k208\10k208.rpt
10k208
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A15 4/ 8( 50%) 4/ 8( 50%) 0/ 8( 0%) 1/2 0/2 3/22( 13%)
A17 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%)
A19 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%)
A20 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
A23 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 1/22( 4%)
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