dmard.tdf

这是用AHDL语言编写的一个PCI采集系统的逻辑源码

CONSTANT sample_data_num = 5000;

SUBDESIGN dmard
(
-- WRITE OPERATION TO NVSRAM, VCC IS AVAILBLE, when it is availble, fifo read is forbid
 	nvsram_write_oe			:	INPUT; 
	sync					:	INPUT;
--input from 10k144 interface
 	bpclk					: 	INPUT;
 	wrfull					: 	INPUT;
--pingpang interface controls
 	addr[14..0]				: 	OUTPUT; 
--data from ram
 	rd_data[7..0]			: 	INPUT;
--signals to 10k144 
 	valid					: 	OUTPUT;
 	trans_data[7..0]		: 	BIDIR;
--	start_read_id : output;
)

VARIABLE
 	start_read_id 			: 	DFF;
	rd_addr[14..0]			: 	DFF;
 	count[13..0]			: 	DFF;
 	valid					: 	DFF;
 	t_data[7..0]			: 	TRI;
	t2_data[7..0]			:	DFF;
	trans_data_dff[7..0]	: 	DFF;
	start_read_id_reset 	: 	DFF;
--read states machine
	trans_control			: 	MACHINE WITH STATES
								(
									asm_idle,t_idle, t_start, 
				 					t_read,t_wait_one, t_wait_two, 
									t_wait_three,t_wait_four
								);
 
BEGIN
DEFAULTS
	start_read_id_reset = VCC;
END DEFAULTS;

  	rd_addr[].clk = bpclk;
 	addr[] = rd_addr[];

	count[].clk = bpclk;

	trans_data_dff[].clk = bpclk;
	t2_data[].clk = bpclk;
	t2_data[] = trans_data_dff[];
	t_data[].oe = !nvsram_write_oe;
	t_data[].in = t2_data[];

	trans_data[] = t_data[].out;
 	valid.clk = bpclk;

 	trans_control.clk = bpclk;
 	trans_control.reset = GND;
	start_read_id.clk = !sync;
	start_read_id = VCC;
	start_read_id.clrn = start_read_id_reset;

	start_read_id_reset.clk = bpclk;
	CASE trans_control IS
		WHEN asm_idle =>
			valid = GND;
			rd_addr[] = 0;	
 			count[] = 0;
			trans_data_dff[] = 0;
			IF(nvsram_write_oe) THEN  -- when write nvsram, read from sram is forbided
				trans_control = asm_idle;
			ELSIF(start_read_id) THEN
				trans_control = t_idle;
			ELSE
				trans_control = asm_idle;
			END IF;
		WHEN t_idle =>
			start_read_id_reset = GND;
			valid = GND;
			rd_addr[] = 0;	
	 		count[] = 0;
			trans_data_dff[] = 0;
			trans_control = t_start;
	    WHEN t_start =>
			start_read_id_reset = VCC;
			valid = GND;
			rd_addr[] = 0;
			count[] = 0;
			trans_data_dff[] = 0;
			IF(wrfull) THEN
				trans_control = t_idle;
			ELSE
				trans_control = t_read;
			END IF;
	  	WHEN t_read =>
			valid = gnd;
	       	rd_addr[] = rd_addr[] + 1;
	       	count[] = count[] + 1;
			----*************************
			--trans_data_dff[] = rd_data[];
			----*************************	   		
			trans_data_dff[] = trans_data_dff[];
			----*************************
			trans_control = t_wait_one;
	   	WHEN t_wait_one =>
			valid = vcc; 
	        rd_addr[] = rd_addr[];  				
			count[] = count[];
			trans_data_dff[] = rd_data[];	
			--trans_data_dff[] = trans_data_dff[];				
	        IF(count[]>=sample_data_num) THEN				
				trans_control = asm_idle;
			ELSE
				trans_control = t_wait_two;
			END IF;
	   	WHEN t_wait_two =>
			valid = GND; 
	        rd_addr[] = rd_addr[];  				
			count[] = count[];	
			trans_data_dff[] = trans_data_dff[];				
			trans_control = t_wait_three;
	   	WHEN t_wait_three =>
			valid = GND;	
    	    rd_addr[] = rd_addr[];  				
			count[] = count[];
			trans_data_dff[] = trans_data_dff[];					
			trans_control = t_wait_four;
   		WHEN t_wait_four =>
			valid = GND;
    	    rd_addr[] = rd_addr[];  				
			count[] = count[];
			trans_data_dff[] = trans_data_dff[];					
			IF(wrfull) THEN
				trans_control = t_wait_four;
			ELSE
				trans_control = t_read;
			END IF;
	 	WHEN OTHERS =>
			valid = GND;
	        rd_addr[] = 0;
		 	count[] = 0;
			trans_data_dff[] = 0;
			trans_control = t_idle;
	END CASE;

END;