10k208.hif

这是用AHDL语言编写的一个PCI采集系统的逻辑源码

HIF003
--
-- Copyright (C) 1988-2000 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner.  Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors.  No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
--
-- Warning: do not edit this file!
--
FILES
{
	f74163.gdf
	{
		f74163 [] []
		{
			14 [] [];
		}
	}
	74163.tdf
	{
		74163 [DEVICE_FAMILY,USE_LPM_FOR_AHDL_OPERATORS] [aglobal.inc]
		{
			13 [DEVICE_FAMILY=FLEX10K,USE_LPM_FOR_AHDL_OPERATORS=OFF] [LDN,CLRN,CLK,ENP,ENT,D,C,B,QA,A];
		}
	}
	16cudslr.gdf
	{
		16cudslr [] []
		{
			11 [] [];
		}
	}
	ceshi.tdf
	{
		ceshi [USE_LPM_FOR_AHDL_OPERATORS] []
		{
			6 [USE_LPM_FOR_AHDL_OPERATORS=OFF] [ceshi0,ceshi1,ceshi2,ceshi3,ceshi4,ceshi5,ceshi6,ceshi7,sm_clk];
		}
	}
	dmard.tdf
	{
		dmard [USE_LPM_FOR_AHDL_OPERATORS] []
		{
			10 [USE_LPM_FOR_AHDL_OPERATORS=OFF] [rd,trans_data0,trans_data1,trans_data2,trans_data3,trans_data4,trans_data5,trans_data6,trans_data7,valid,rd_data0,rd_data1,rd_data2,rd_data3,rd_data4,rd_data5,rd_data6,rd_data7,addr0,addr1,addr2,addr3,addr4,addr5,addr6,addr7,addr8,addr9,addr10,addr11,addr12,addr13,addr14,wrfull,bpclk,sync,nvsram_write_oe];
			9 [USE_LPM_FOR_AHDL_OPERATORS=OFF] [trans_data0,trans_data1,trans_data2,trans_data3,trans_data4,trans_data5,trans_data6,trans_data7,valid,rd_data0,rd_data1,rd_data2,rd_data3,rd_data4,rd_data5,rd_data6,rd_data7,addr0,addr1,addr2,addr3,addr4,addr5,addr6,addr7,addr8,addr9,addr10,addr11,addr12,addr13,addr14,wrfull,bpclk,sync,nvsram_write_oe];
			2 [USE_LPM_FOR_AHDL_OPERATORS=OFF] [trans_data0,trans_data1,trans_data2,trans_data3,trans_data4,trans_data5,trans_data6,trans_data7,valid,rd_data0,rd_data1,rd_data2,rd_data3,rd_data4,rd_data5,rd_data6,rd_data7,addr0,addr1,addr2,addr3,addr4,addr5,addr6,addr7,addr8,addr9,addr10,addr11,addr12,wrfull,bpclk,sync,NVSRAM_WRITE_OE];
			1 [USE_LPM_FOR_AHDL_OPERATORS=OFF] [trans_data0,trans_data1,trans_data2,trans_data3,trans_data4,trans_data5,trans_data6,trans_data7,rd_data0,rd_data1,rd_data2,rd_data3,rd_data4,rd_data5,rd_data6,rd_data7,wrfull,bpclk,sync,NVSRAM_WRITE_OE];
		}
	}
	datasample.tdf
	{
		datasample [USE_LPM_FOR_AHDL_OPERATORS] []
		{
			15 [USE_LPM_FOR_AHDL_OPERATORS=OFF] [pclk,sync,ndfv,dfv,ram_wr_addr0,ram_wr_addr1,ram_wr_addr2,ram_wr_addr3,ram_wr_addr4,ram_wr_addr5,ram_wr_addr6,ram_wr_addr7,ram_wr_addr8,ram_wr_addr9,ram_wr_addr10,ram_wr_addr11,ram_wr_addr12,ram_wr_addr13,ram_wr_addr14,data_out0,data_out1,data_out2,data_out3,data_out4,data_out5,data_out6,data_out7,src_clk,sm_clk,data_in0,data_in1,data_in2,data_in3,data_in4,data_in5,data_in6,data_in7,sh];
			7 [USE_LPM_FOR_AHDL_OPERATORS=OFF] [pclk,sync,ndfv,dfv,ram_wr,ram_wr_addr0,ram_wr_addr1,ram_wr_addr2,ram_wr_addr3,ram_wr_addr4,ram_wr_addr5,ram_wr_addr6,ram_wr_addr7,ram_wr_addr8,ram_wr_addr9,ram_wr_addr10,ram_wr_addr11,ram_wr_addr12,ram_wr_addr13,ram_wr_addr14,data_out0,data_out1,data_out2,data_out3,data_out4,data_out5,data_out6,data_out7,src_clk,sm_clk,data_in0,data_in1,data_in2,data_in3,data_in4,data_in5,data_in6,data_in7,sh];
			3 [USE_LPM_FOR_AHDL_OPERATORS=OFF] [PCLK,SYNC,NDFV,DFV,RAM_WR,RAM_WR_ADDR0,RAM_WR_ADDR1,RAM_WR_ADDR2,RAM_WR_ADDR3,RAM_WR_ADDR4,RAM_WR_ADDR5,RAM_WR_ADDR6,RAM_WR_ADDR7,RAM_WR_ADDR8,RAM_WR_ADDR9,RAM_WR_ADDR10,RAM_WR_ADDR11,RAM_WR_ADDR12,DATA_OUT0,DATA_OUT1,DATA_OUT2,DATA_OUT3,DATA_OUT4,DATA_OUT5,DATA_OUT6,DATA_OUT7,SRC_CLK,SM_CLK,DATA_IN0,DATA_IN1,DATA_IN2,DATA_IN3,DATA_IN4,DATA_IN5,DATA_IN6,DATA_IN7,SH];
		}
	}
	nvsram.tdf
	{
		nvsram [USE_LPM_FOR_AHDL_OPERATORS] []
		{
			4 [USE_LPM_FOR_AHDL_OPERATORS=OFF] [TM_WE/,TMA0,TMA1,TMA2,TMA3,TMA4,TMA5,TMA6,TMA7,TMA8,TMA9,TMA10,TMA11,TMA12,TMA13,TMA14,TMA15,TMA16,TM_OE/,TM_WR/,WR_ADDRESS0,WR_ADDRESS1,WR_ADDRESS2,WR_ADDRESS3,WR_ADDRESS4,WR_ADDRESS5,WR_ADDRESS6,WR_ADDRESS7,WR_ADDRESS8,WR_ADDRESS9,WR_ADDRESS10,WR_ADDRESS11,WR_ADDRESS12,WR_ADDRESS13,WR_ADDRESS14,WR_ADDRESS15,WR_ADDRESS16,NVSRAM_WRITE_OE,TMD0,TMD1,TMD2,TMD3,TMD4,TMD5,TMD6,TMD7,DATA0,DATA1,DATA2,DATA3,DATA4,DATA5,DATA6,DATA7,SRC_CLK];
		}
	}
	pingp.tdf
	{
		pingp [USE_LPM_FOR_AHDL_OPERATORS] []
		{
			16 [USE_LPM_FOR_AHDL_OPERATORS=OFF] [rd_data0,rd_data1,rd_data2,rd_data3,rd_data4,rd_data5,rd_data6,rd_data7,ramb_oe,rama_oe,ramb_addr0,ramb_addr1,ramb_addr2,ramb_addr3,ramb_addr4,ramb_addr5,ramb_addr6,ramb_addr7,ramb_addr8,ramb_addr9,ramb_addr10,ramb_addr11,ramb_addr12,ramb_addr13,ramb_addr14,rama_addr0,rama_addr1,rama_addr2,rama_addr3,rama_addr4,rama_addr5,rama_addr6,rama_addr7,rama_addr8,rama_addr9,rama_addr10,rama_addr11,rama_addr12,rama_addr13,rama_addr14,ramb_data0,ramb_data1,ramb_data2,ramb_data3,ramb_data4,ramb_data5,ramb_data6,ramb_data7,rama_data0,rama_data1,rama_data2,rama_data3,rama_data4,rama_data5,rama_data6,rama_data7,ramb_wr,rama_wr,rd_addr0,rd_addr1,rd_addr2,rd_addr3,rd_addr4,rd_addr5,rd_addr6,rd_addr7,rd_addr8,rd_addr9,rd_addr10,rd_addr11,rd_addr12,rd_addr13,rd_addr14,ndfv,dfv,wr_clk,wr_addr0,wr_addr1,wr_addr2,wr_addr3,wr_addr4,wr_addr5,wr_addr6,wr_addr7,wr_addr8,wr_addr9,wr_addr10,wr_addr11,wr_addr12,wr_addr13,wr_addr14,wr_data0,wr_data1,wr_data2,wr_data3,wr_data4,wr_data5,wr_data6,wr_data7];
			12 [USE_LPM_FOR_AHDL_OPERATORS=OFF] [rd_data0,rd_data1,rd_data2,rd_data3,rd_data4,rd_data5,rd_data6,rd_data7,ramb_oe,rama_oe,ramb_addr0,ramb_addr1,ramb_addr2,ramb_addr3,ramb_addr4,ramb_addr5,ramb_addr6,ramb_addr7,ramb_addr8,ramb_addr9,ramb_addr10,ramb_addr11,ramb_addr12,ramb_addr13,ramb_addr14,ramb_data0,ramb_data1,ramb_data2,ramb_data3,ramb_data4,ramb_data5,ramb_data6,ramb_data7,rama_data0,rama_data1,rama_data2,rama_data3,rama_data4,rama_data5,rama_data6,rama_data7,ramb_wr,rama_wr,rd_clk,rd_addr0,rd_addr1,rd_addr2,rd_addr3,rd_addr4,rd_addr5,rd_addr6,rd_addr7,rd_addr8,rd_addr9,rd_addr10,rd_addr11,rd_addr12,rd_addr13,rd_addr14,sync,ndfv,dfv,wr,wr_clk,wr_addr0,wr_addr1,wr_addr2,wr_addr3,wr_addr4,wr_addr5,wr_addr6,wr_addr7,wr_addr8,wr_addr9,wr_addr10,wr_addr11,wr_addr12,wr_addr13,wr_addr14,wr_data0,wr_data1,wr_data2,wr_data3,wr_data4,wr_data5,wr_data6,wr_data7];
			8 [USE_LPM_FOR_AHDL_OPERATORS=OFF] [rd_data0,rd_data1,rd_data2,rd_data3,rd_data4,rd_data5,rd_data6,rd_data7,ramb_oe,rama_oe,ramb_addr0,ramb_addr1,ramb_addr2,ramb_addr3,ramb_addr4,ramb_addr5,ramb_addr6,ramb_addr7,ramb_addr8,ramb_addr9,ramb_addr10,ramb_addr11,ramb_addr12,ramb_addr13,ramb_addr14,rama_addr0,rama_addr1,rama_addr2,rama_addr3,rama_addr4,rama_addr5,rama_addr6,rama_addr7,rama_addr8,rama_addr9,rama_addr10,rama_addr11,rama_addr12,rama_addr13,rama_addr14,ramb_data0,ramb_data1,ramb_data2,ramb_data3,ramb_data4,ramb_data5,ramb_data6,ramb_data7,rama_data0,rama_data1,rama_data2,rama_data3,rama_data4,rama_data5,rama_data6,rama_data7,ramb_wr,rama_wr,rd_clk,rd_addr0,rd_addr1,rd_addr2,rd_addr3,rd_addr4,rd_addr5,rd_addr6,rd_addr7,rd_addr8,rd_addr9,rd_addr10,rd_addr11,rd_addr12,rd_addr13,rd_addr14,sync,ndfv,dfv,wr,wr_clk,wr_addr0,wr_addr1,wr_addr2,wr_addr3,wr_addr4,wr_addr5,wr_addr6,wr_addr7,wr_addr8,wr_addr9,wr_addr10,wr_addr11,wr_addr12,wr_addr13,wr_addr14,wr_data0,wr_data1,wr_data2,wr_data3,wr_data4,wr_data5,wr_data6,wr_data7];
			5 [USE_LPM_FOR_AHDL_OPERATORS=OFF] [rd_data0,rd_data1,rd_data2,rd_data3,rd_data4,rd_data5,rd_data6,rd_data7,ramb_oe,rama_oe,ramb_addr0,ramb_addr1,ramb_addr2,ramb_addr3,ramb_addr4,ramb_addr5,ramb_addr6,ramb_addr7,ramb_addr8,ramb_addr9,ramb_addr10,ramb_addr11,ramb_addr12,rama_addr0,rama_addr1,rama_addr2,rama_addr3,rama_addr4,rama_addr5,rama_addr6,rama_addr7,rama_addr8,rama_addr9,rama_addr10,rama_addr11,rama_addr12,ramb_data0,ramb_data1,ramb_data2,ramb_data3,ramb_data4,ramb_data5,ramb_data6,ramb_data7,rama_data0,rama_data1,rama_data2,rama_data3,rama_data4,rama_data5,rama_data6,rama_data7,ramb_wr,rama_wr,rd_clk,rd_addr0,rd_addr1,rd_addr2,rd_addr3,rd_addr4,rd_addr5,rd_addr6,rd_addr7,rd_addr8,rd_addr9,rd_addr10,rd_addr11,rd_addr12,sync,ndfv,dfv,wr,wr_clk,wr_addr0,wr_addr1,wr_addr2,wr_addr3,wr_addr4,wr_addr5,wr_addr6,wr_addr7,wr_addr8,wr_addr9,wr_addr10,wr_addr11,wr_addr12,wr_data0,wr_data1,wr_data2,wr_data3,wr_data4,wr_data5,wr_data6,wr_data7];
		}
	}
	10k208.gdf
	{
		10k208 [] []
		{
			0 [] [];
		}
	}
}
TREE
{
	10k208::(0,0):(0): 10k208.gdf
	{
		datasample:7:(0,0):(2): datasample.tdf;
		pingp:8:(0,0):(4): pingp.tdf;
		dmard:9:(0,0):(19): dmard.tdf;
		nvsram::(0,0):(3): nvsram.tdf;
	}
}