📄 dmard.rpt
字号:
70 - - A -- OUTPUT 0 1 0 0 addr10
81 - - - 22 OUTPUT 0 1 0 0 addr11
72 - - A -- OUTPUT 0 1 0 0 addr12
69 - - A -- OUTPUT 0 1 0 0 start_read_id
62 - - C -- TRI 0 1 0 0 trans_data0
73 - - A -- TRI 0 1 0 0 trans_data1
59 - - C -- TRI 0 1 0 0 trans_data2
17 - - A -- TRI 0 1 0 0 trans_data3
58 - - C -- TRI 0 1 0 0 trans_data4
67 - - B -- TRI 0 1 0 0 trans_data5
22 - - B -- TRI 0 1 0 0 trans_data6
24 - - B -- TRI 0 1 0 0 trans_data7
79 - - - 24 OUTPUT 0 1 0 0 valid
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\hanpj\pld\dma\10k208\dmard.rpt
dmard
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - A 24 DFFE + 0 2 0 2 count0
- 3 - A 24 DFFE + 0 3 0 1 count1
- 4 - A 24 DFFE + 0 3 0 3 count2
- 6 - A 18 DFFE + 0 3 0 3 count3
- 4 - A 18 DFFE + 0 3 0 2 count4
- 8 - A 18 DFFE + 0 3 0 2 count5
- 7 - A 18 DFFE + 0 3 0 2 count6
- 6 - A 16 DFFE + 0 3 0 4 count7
- 5 - A 16 DFFE + 0 3 0 3 count8
- 8 - A 16 DFFE + 0 3 0 2 count9
- 1 - A 20 DFFE + 0 3 0 4 count10
- 6 - A 20 DFFE + 0 3 0 3 count11
- 3 - A 20 DFFE + 0 3 0 3 count12
- 4 - A 13 DFFE + 0 3 0 2 count13
- 6 - A 22 DFFE + 0 2 1 3 rd_addr0
- 7 - B 20 DFFE + 0 3 1 2 rd_addr1
- 5 - B 13 DFFE + 0 3 1 1 rd_addr2
- 2 - B 20 DFFE + 0 3 1 3 rd_addr3
- 3 - B 20 DFFE + 0 3 1 2 rd_addr4
- 8 - B 20 DFFE + 0 3 1 1 rd_addr5
- 4 - A 23 DFFE + 0 3 1 3 rd_addr6
- 6 - A 23 DFFE + 0 3 1 2 rd_addr7
- 7 - A 23 DFFE + 0 3 1 1 rd_addr8
- 4 - A 22 DFFE + 0 3 1 3 rd_addr9
- 8 - A 22 DFFE + 0 3 1 2 rd_addr10
- 1 - A 22 DFFE + 0 3 1 1 rd_addr11
- 3 - A 22 DFFE + 0 3 1 0 rd_addr12
- 6 - A 14 DFFE + 0 1 0 1 start_read_id_reset
- 8 - A 13 DFFE + 1 1 0 2 trans_control~1
- 7 - A 13 DFFE + 0 1 0 2 trans_control~2
- 6 - A 13 DFFE + 0 4 0 2 trans_control~3
- 5 - A 13 DFFE + 0 1 0 3 trans_control~4
- 2 - A 13 DFFE + 1 2 0 38 trans_control~5
- 3 - A 14 DFFE + 0 1 0 3 trans_control~6
- 5 - A 14 DFFE + 1 3 0 3 trans_control~7
- 1 - A 14 DFFE + 1 2 0 2 trans_control~8
- 2 - C 16 DFFE + 1 2 0 1 trans_data_dff0
- 7 - A 24 DFFE + 1 2 0 1 trans_data_dff1
- 1 - C 20 DFFE + 1 2 0 1 trans_data_dff2
- 1 - A 23 DFFE + 1 2 0 1 trans_data_dff3
- 1 - C 23 DFFE + 1 2 0 1 trans_data_dff4
- 3 - B 13 DFFE + 1 2 0 1 trans_data_dff5
- 4 - B 13 DFFE + 1 2 0 1 trans_data_dff6
- 7 - B 13 DFFE + 1 2 0 1 trans_data_dff7
- 1 - C 16 DFFE + 0 1 1 0 t2_data0
- 1 - A 24 DFFE + 0 1 1 0 t2_data1
- 8 - C 20 DFFE + 0 1 1 0 t2_data2
- 3 - A 23 DFFE + 0 1 1 0 t2_data3
- 7 - C 23 DFFE + 0 1 1 0 t2_data4
- 1 - B 13 DFFE + 0 1 1 0 t2_data5
- 2 - B 13 DFFE + 0 1 1 0 t2_data6
- 6 - B 13 DFFE + 0 1 1 0 t2_data7
- 5 - A 24 DFFE + 0 1 1 0 :62
- 8 - A 14 DFFE + 0 1 1 2 :63
- 8 - B 13 AND2 0 2 0 1 :179
- 4 - B 20 AND2 0 3 0 4 :183
- 5 - B 20 AND2 0 2 0 1 :187
- 6 - B 20 AND2 0 3 0 1 :191
- 1 - B 20 AND2 0 4 0 4 :195
- 5 - A 23 AND2 0 2 0 1 :199
- 8 - A 23 AND2 0 3 0 1 :203
- 2 - A 23 AND2 0 4 0 4 :207
- 2 - A 22 AND2 0 2 0 1 :211
- 5 - A 22 AND2 0 3 0 1 :215
- 7 - A 22 AND2 0 4 0 1 :219
- 8 - A 24 AND2 0 2 0 4 :243
- 2 - A 24 AND2 0 2 0 1 :247
- 3 - A 18 AND2 0 3 0 1 :251
- 1 - A 18 AND2 0 4 0 2 :255
- 2 - A 18 AND2 0 2 0 2 :259
- 3 - A 16 AND2 0 2 0 4 :263
- 4 - A 16 AND2 0 2 0 1 :267
- 7 - A 16 AND2 0 3 0 1 :271
- 2 - A 16 AND2 0 4 0 4 :275
- 4 - A 20 AND2 0 2 0 1 :279
- 7 - A 20 AND2 0 3 0 1 :283
- 2 - A 20 AND2 0 4 0 1 :287
- 5 - A 18 AND2 ! 0 4 0 1 :391
- 1 - A 16 OR2 s 0 3 0 1 ~398~1
- 5 - A 20 OR2 ! 0 4 0 2 :400
- 1 - A 13 OR2 ! 0 4 0 1 :405
- 2 - A 14 AND2 s 0 4 0 1 ~562~1
- 3 - A 13 OR2 s 0 4 0 36 ~590~1
- 4 - A 14 OR2 s 1 3 0 1 ~648~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\hanpj\pld\dma\10k208\dmard.rpt
dmard
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 3/ 96( 3%) 0/ 48( 0%) 22/ 48( 45%) 1/16( 6%) 5/16( 31%) 2/16( 12%)
B: 6/ 96( 6%) 0/ 48( 0%) 6/ 48( 12%) 3/16( 18%) 3/16( 18%) 3/16( 18%)
C: 2/ 96( 2%) 0/ 48( 0%) 5/ 48( 10%) 2/16( 12%) 0/16( 0%) 3/16( 18%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\hanpj\pld\dma\10k208\dmard.rpt
dmard
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 53 bpclk
INPUT 1 sync
Device-Specific Information: e:\hanpj\pld\dma\10k208\dmard.rpt
dmard
** CLEAR SIGNALS **
Type Fan-out Name
DFF 1 start_read_id_reset
Device-Specific Information: e:\hanpj\pld\dma\10k208\dmard.rpt
dmard
** EQUATIONS **
bpclk : INPUT;
NVSRAM_WRITE_OE : INPUT;
rd_data0 : INPUT;
rd_data1 : INPUT;
rd_data2 : INPUT;
rd_data3 : INPUT;
rd_data4 : INPUT;
rd_data5 : INPUT;
rd_data6 : INPUT;
rd_data7 : INPUT;
sync : INPUT;
wrfull : INPUT;
-- Node name is 'addr0' from file "dmard.tdf" line 42, column 7
-- Equation name is 'addr0', type is output
addr0 = rd_addr0;
-- Node name is 'addr1' from file "dmard.tdf" line 42, column 7
-- Equation name is 'addr1', type is output
addr1 = rd_addr1;
-- Node name is 'addr2' from file "dmard.tdf" line 42, column 7
-- Equation name is 'addr2', type is output
addr2 = rd_addr2;
-- Node name is 'addr3' from file "dmard.tdf" line 42, column 7
-- Equation name is 'addr3', type is output
addr3 = rd_addr3;
-- Node name is 'addr4' from file "dmard.tdf" line 42, column 7
-- Equation name is 'addr4', type is output
addr4 = rd_addr4;
-- Node name is 'addr5' from file "dmard.tdf" line 42, column 7
-- Equation name is 'addr5', type is output
addr5 = rd_addr5;
-- Node name is 'addr6' from file "dmard.tdf" line 42, column 7
-- Equation name is 'addr6', type is output
addr6 = rd_addr6;
-- Node name is 'addr7' from file "dmard.tdf" line 42, column 7
-- Equation name is 'addr7', type is output
addr7 = rd_addr7;
-- Node name is 'addr8' from file "dmard.tdf" line 42, column 7
-- Equation name is 'addr8', type is output
addr8 = rd_addr8;
-- Node name is 'addr9' from file "dmard.tdf" line 42, column 7
-- Equation name is 'addr9', type is output
addr9 = rd_addr9;
-- Node name is 'addr10' from file "dmard.tdf" line 42, column 7
-- Equation name is 'addr10', type is output
addr10 = rd_addr10;
-- Node name is 'addr11' from file "dmard.tdf" line 42, column 7
-- Equation name is 'addr11', type is output
addr11 = rd_addr11;
-- Node name is 'addr12' from file "dmard.tdf" line 42, column 7
-- Equation name is 'addr12', type is output
addr12 = rd_addr12;
-- Node name is 'count0' from file "dmard.tdf" line 24, column 8
-- Equation name is 'count0', location is LC6_A24, type is buried.
count0 = DFFE( _EQ001, GLOBAL( bpclk), VCC, VCC, VCC);
_EQ001 = count0 & _LC3_A13
# !count0 & trans_control~5;
-- Node name is 'count1' from file "dmard.tdf" line 24, column 8
-- Equation name is 'count1', location is LC3_A24, type is buried.
count1 = DFFE( _EQ002, GLOBAL( bpclk), VCC, VCC, VCC);
_EQ002 = count1 & _LC3_A13
# count0 & !count1 & trans_control~5
# !count0 & count1 & trans_control~5;
-- Node name is 'count2' from file "dmard.tdf" line 24, column 8
-- Equation name is 'count2', location is LC4_A24, type is buried.
count2 = DFFE( _EQ003, GLOBAL( bpclk), VCC, VCC, VCC);
_EQ003 = count2 & !_LC8_A24 & trans_control~5
# !count2 & _LC8_A24 & trans_control~5
# count2 & _LC3_A13;
-- Node name is 'count3' from file "dmard.tdf" line 24, column 8
-- Equation name is 'count3', location is LC6_A18, type is buried.
count3 = DFFE( _EQ004, GLOBAL( bpclk), VCC, VCC, VCC);
_EQ004 = count3 & _LC3_A13
# count3 & !_LC2_A24 & trans_control~5
# !count3 & _LC2_A24 & trans_control~5;
-- Node name is 'count4' from file "dmard.tdf" line 24, column 8
-- Equation name is 'count4', location is LC4_A18, type is buried.
count4 = DFFE( _EQ005, GLOBAL( bpclk), VCC, VCC, VCC);
_EQ005 = count4 & _LC3_A13
# count4 & !_LC3_A18 & trans_control~5
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