📄 dmard.rpt
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Project Information e:\hanpj\pld\dma\10k208\dmard.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 05/25/2003 20:32:38
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
Untitled
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
dmard EPF10K10LC84-3 12 15 8 0 0 % 84 14 %
User Pins: 12 15 8
Project Information e:\hanpj\pld\dma\10k208\dmard.rpt
** STATE MACHINE ASSIGNMENTS **
trans_control: MACHINE
OF BITS (
trans_control~8,
trans_control~7,
trans_control~6,
trans_control~5,
trans_control~4,
trans_control~3,
trans_control~2,
trans_control~1
)
WITH STATES (
asm_idle = B"00000000",
t_idle = B"11000000",
t_start = B"10100000",
t_read = B"10010000",
t_wait_one = B"10001000",
t_wait_two = B"10000100",
t_wait_three = B"10000010",
t_wait_four = B"10000001"
);
Device-Specific Information: e:\hanpj\pld\dma\10k208\dmard.rpt
dmard
***** Logic for device 'dmard' compiled without errors.
Device: EPF10K10LC84-3
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
N
V
S
R
A
M ^
_ C
R R R R R R R R W r R O
E E E E E E E E R d E N
S S S S S S S V S I _ S G a F
E E E E E E E C E T b d E N d a v a _ ^
R R R R R R R C R E p a R D d d a d # D n
V V V V V V V I V _ c t V I r d l d T O C
E E E E E E E N E O l a E N 1 r i r C N E
D D D D D D D T D E k 1 D T 1 7 d 6 K E O
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
^DATA0 | 12 74 | #TDO
^DCLK | 13 73 | trans_data1
^nCE | 14 72 | addr12
#TDI | 15 71 | addr9
RESERVED | 16 70 | addr10
trans_data3 | 17 69 | start_read_id
rd_data3 | 18 68 | GNDINT
addr8 | 19 67 | trans_data5
VCCINT | 20 66 | addr3
rd_data7 | 21 65 | addr2
trans_data6 | 22 EPF10K10LC84-3 64 | addr1
rd_data5 | 23 63 | VCCINT
trans_data7 | 24 62 | trans_data0
rd_data6 | 25 61 | rd_data4
GNDINT | 26 60 | RESERVED
RESERVED | 27 59 | trans_data2
RESERVED | 28 58 | trans_data4
rd_data2 | 29 57 | #TMS
RESERVED | 30 56 | #TRST
^MSEL0 | 31 55 | ^nSTATUS
^MSEL1 | 32 54 | addr0
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
V ^ R R R R R V G w s r V G R R R R R a a
C n E E E E E C N r y d C N E E E E E d d
C C S S S S S C D f n _ C D S S S S S d d
I O E E E E E I I u c d I I E E E E E r r
N N R R R R R N N l a N N R R R R R 5 4
T F V V V V V T T l t T T V V V V V
I E E E E E a E E E E E
G D D D D D 0 D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: e:\hanpj\pld\dma\10k208\dmard.rpt
dmard
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A13 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 1/2 0/2 5/22( 22%)
A14 7/ 8( 87%) 0/ 8( 0%) 2/ 8( 25%) 2/2 1/2 5/22( 22%)
A16 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 4/22( 18%)
A18 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 5/22( 22%)
A20 7/ 8( 87%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 5/22( 22%)
A22 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 1/2 0/2 3/22( 13%)
A23 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 1/2 0/2 4/22( 18%)
A24 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 3/22( 13%)
B13 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 7/22( 31%)
B20 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 1/2 0/2 4/22( 18%)
C16 2/ 8( 25%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 3/22( 13%)
C20 2/ 8( 25%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 3/22( 13%)
C23 2/ 8( 25%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 3/22( 13%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 29/53 ( 54%)
Total logic cells used: 84/576 ( 14%)
Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 3.10/4 ( 77%)
Total fan-in: 261/2304 ( 11%)
Total input pins required: 12
Total input I/O cell registers required: 0
Total output pins required: 15
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 8
Total reserved pins required 0
Total logic cells required: 84
Total flipflops required: 54
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 4/ 576 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 8 7 0 8 0 8 0 7 0 8 8 8 62/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 8 0 0 0 0 16/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 2 0 0 2 0 6/0
Total: 0 0 0 0 0 0 0 0 0 0 0 0 0 16 7 0 10 0 8 0 17 0 8 10 8 84/0
Device-Specific Information: e:\hanpj\pld\dma\10k208\dmard.rpt
dmard
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
1 - - - -- INPUT G 0 0 0 0 bpclk
2 - - - -- INPUT G 0 0 0 2 NVSRAM_WRITE_OE
44 - - - -- INPUT 0 0 0 1 rd_data0
84 - - - -- INPUT 0 0 0 1 rd_data1
29 - - C -- INPUT 0 0 0 1 rd_data2
18 - - A -- INPUT 0 0 0 1 rd_data3
61 - - C -- INPUT 0 0 0 1 rd_data4
23 - - B -- INPUT 0 0 0 1 rd_data5
25 - - B -- INPUT 0 0 0 1 rd_data6
21 - - B -- INPUT 0 0 0 1 rd_data7
43 - - - -- INPUT G 0 0 0 0 sync
62 - - C -- BIDIR 0 1 0 0 trans_data0
73 - - A -- BIDIR 0 1 0 0 trans_data1
59 - - C -- BIDIR 0 1 0 0 trans_data2
17 - - A -- BIDIR 0 1 0 0 trans_data3
58 - - C -- BIDIR 0 1 0 0 trans_data4
67 - - B -- BIDIR 0 1 0 0 trans_data5
22 - - B -- BIDIR 0 1 0 0 trans_data6
24 - - B -- BIDIR 0 1 0 0 trans_data7
42 - - - -- INPUT 0 0 0 3 wrfull
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\hanpj\pld\dma\10k208\dmard.rpt
dmard
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
54 - - - 21 OUTPUT 0 1 0 0 addr0
64 - - B -- OUTPUT 0 1 0 0 addr1
65 - - B -- OUTPUT 0 1 0 0 addr2
66 - - B -- OUTPUT 0 1 0 0 addr3
53 - - - 20 OUTPUT 0 1 0 0 addr4
52 - - - 19 OUTPUT 0 1 0 0 addr5
78 - - - 24 OUTPUT 0 1 0 0 addr6
80 - - - 23 OUTPUT 0 1 0 0 addr7
19 - - A -- OUTPUT 0 1 0 0 addr8
71 - - A -- OUTPUT 0 1 0 0 addr9
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