📄 datasample.tdf
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SUBDESIGN datasample
(
--signals from data sample circuit
sh : INPUT; -- line CCD frame sync
data_in[7..0] : INPUT; -- CA3318 data output(ID[7..0])
sm_clk : INPUT; -- CA3318 SAMPLE CLK
src_clk : INPUT; -- SOURCE CLK,TO PRODUCE TIMING SIGNALS ,10M
--signals to pingpang unit
data_out[7..0] : OUTPUT;
ram_wr_addr[14..0] : OUTPUT;
dfv,ndfv,sync,pclk : OUTPUT; --ODD AND EVEN INDICATOR
)
VARIABLE
o_e,pclk : DFF;
data[7..0] : DFF;
ram_wr_addr[14..0] : DFF;
BEGIN
--produce wr ouput
sync = sh;
pclk.clk = !src_clk;
pclk = sm_clk;
--produce data output
data[].clk = pclk;
data[] = data_in[];
data_out[] = data[];
--produce addr output
ram_wr_addr[].clk = PCLK;
ram_wr_addr[] = ram_wr_addr[] + 1;
ram_wr_addr[].clrn = !sh;
--ram_wr_addr[] = ram_addr;
--PRODUCE ODD AND EVEN SIGNALS
o_e.clk = sh;
o_e = !o_e;
dfv = o_e;
ndfv = !o_e;
END;
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