nvsram.tdf

来自「这是用AHDL语言编写的一个PCI采集系统的逻辑源码」· TDF 代码 · 共 45 行

SUBDESIGN NVSRAM
(

	src_clk				:	INPUT;  -- SELF CLOCK 10M
	data[7..0]			:	INPUT;  -- DATA FROM PCI BUS
	tmd[7..0]			:	BIDIR;  -- NVSRAM DATA BUS
	nvsram_write_oe		:	INPUT;  -- WRITE OPERATION TO NVSRAM, VCC IS AVAILBLE
	wr_address[16..0]	:	INPUT;
	tm_wr/				:	INPUT;  --WRITE TIME PROGRAM FROM PCI TO NVSRAM
	tm_oe/				:	OUTPUT;  -- NVSRAM OUTPUT ENABLE
	tma[16..0]			:	OUTPUT;  -- NVSRAM ADDRESS BUS
	tm_we/				:	OUTPUT;
)

VARIABLE
 	rd_address[16..0]	:	DFF;
	temp_data[7..0]		:	TRI;

BEGIN
	
	rd_address[].clk = src_clk;
	rd_address[].clrn = !nvsram_write_oe; -- WHEN WRITE TO NVSRAM, READ ADDRESS IS CLEAR TO 0
	
	IF rd_address[] == 50781 THEN
		rd_address[] = 0;
	ELSE
		rd_address[] = rd_address[] +1;
	END IF;
	
	tm_oe/ = nvsram_write_oe;
	tm_we/ = tm_wr/;    -- PRODUCED BY PCI,MUST WAIT 3 STATE, NVSRAM IS 70 NS WRITE CYCLE

	IF nvsram_write_oe == VCC THEN
		tma[] = wr_address[];
	ELSE
		tma[16..0] = rd_address[16..0];
	END IF;
	
   	temp_data[].oe = nvsram_write_oe;
	temp_data[].in = data[];
	tmd[] = temp_data[].out;

END;