📄 pingp.rpt
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203 - - - 21 INPUT 0 0 0 2 wr_addr7
190 - - - 15 INPUT 0 0 0 2 wr_addr8
166 - - - 05 INPUT 0 0 0 2 wr_addr9
148 - - A -- INPUT 0 0 0 2 wr_addr10
18 - - A -- INPUT 0 0 0 2 wr_addr11
135 - - B -- INPUT 0 0 0 2 wr_addr12
46 - - C -- INPUT 0 0 0 2 wr_clk
182 - - - -- INPUT 0 0 0 2 wr_data0
184 - - - -- INPUT 0 0 0 2 wr_data1
79 - - - -- INPUT 0 0 0 2 wr_data2
183 - - - -- INPUT 0 0 0 2 wr_data3
38 - - C -- INPUT 0 0 0 2 wr_data4
95 - - - 06 INPUT 0 0 0 2 wr_data5
63 - - - 19 INPUT 0 0 0 2 wr_data6
160 - - - 02 INPUT 0 0 0 2 wr_data7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\hanpj\pld\dma\10k208\pingp.rpt
pingp
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
47 - - C -- OUTPUT 0 1 0 0 rama_addr0
208 - - - 24 OUTPUT 0 1 0 0 rama_addr1
29 - - B -- OUTPUT 0 1 0 0 rama_addr2
94 - - - 07 OUTPUT 0 1 0 0 rama_addr3
141 - - A -- OUTPUT 0 1 0 0 rama_addr4
92 - - - 08 OUTPUT 0 1 0 0 rama_addr5
103 - - - 01 OUTPUT 0 1 0 0 rama_addr6
199 - - - 20 OUTPUT 0 1 0 0 rama_addr7
30 - - B -- OUTPUT 0 1 0 0 rama_addr8
162 - - - 03 OUTPUT 0 1 0 0 rama_addr9
16 - - A -- OUTPUT 0 1 0 0 rama_addr10
12 - - A -- OUTPUT 0 1 0 0 rama_addr11
101 - - - 03 OUTPUT 0 1 0 0 rama_addr12
19 - - A -- TRI 0 1 0 1 rama_data0
150 - - A -- TRI 0 1 0 1 rama_data1
132 - - B -- TRI 0 1 0 1 rama_data2
45 - - C -- TRI 0 1 0 1 rama_data3
115 - - C -- TRI 0 1 0 1 rama_data4
121 - - C -- TRI 0 1 0 1 rama_data5
27 - - B -- TRI 0 1 0 1 rama_data6
128 - - B -- TRI 0 1 0 1 rama_data7
112 - - C -- OUTPUT 0 1 0 0 rama_oe
187 - - - 13 OUTPUT 0 1 0 0 rama_wr
193 - - - 17 OUTPUT 0 1 0 0 ramb_addr0
207 - - - 24 OUTPUT 0 1 0 0 ramb_addr1
24 - - B -- OUTPUT 0 1 0 0 ramb_addr2
127 - - B -- OUTPUT 0 1 0 0 ramb_addr3
149 - - A -- OUTPUT 0 1 0 0 ramb_addr4
170 - - - 08 OUTPUT 0 1 0 0 ramb_addr5
104 - - - 01 OUTPUT 0 1 0 0 ramb_addr6
200 - - - 20 OUTPUT 0 1 0 0 ramb_addr7
28 - - B -- OUTPUT 0 1 0 0 ramb_addr8
147 - - A -- OUTPUT 0 1 0 0 ramb_addr9
10 - - A -- OUTPUT 0 1 0 0 ramb_addr10
13 - - A -- OUTPUT 0 1 0 0 ramb_addr11
133 - - B -- OUTPUT 0 1 0 0 ramb_addr12
17 - - A -- TRI 0 1 0 1 ramb_data0
143 - - A -- TRI 0 1 0 1 ramb_data1
131 - - B -- TRI 0 1 0 1 ramb_data2
39 - - C -- TRI 0 1 0 1 ramb_data3
111 - - C -- TRI 0 1 0 1 ramb_data4
116 - - C -- TRI 0 1 0 1 ramb_data5
26 - - B -- TRI 0 1 0 1 ramb_data6
136 - - B -- TRI 0 1 0 1 ramb_data7
189 - - - 14 OUTPUT 0 1 0 0 ramb_oe
41 - - C -- OUTPUT 0 1 0 0 ramb_wr
100 - - - 03 OUTPUT 0 1 0 0 rd_data0
206 - - - 23 OUTPUT 0 1 0 0 rd_data1
64 - - - 18 OUTPUT 0 1 0 0 rd_data2
122 - - C -- OUTPUT 0 1 0 0 rd_data3
74 - - - 13 OUTPUT 0 1 0 0 rd_data4
40 - - C -- OUTPUT 0 1 0 0 rd_data5
31 - - B -- OUTPUT 0 1 0 0 rd_data6
25 - - B -- OUTPUT 0 1 0 0 rd_data7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\hanpj\pld\dma\10k208\pingp.rpt
pingp
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 8 - A 16 LCELL s 1 0 1 0 data_outa0~1
- 1 - A 07 LCELL s 1 0 1 0 data_outa1~1
- 8 - B 12 LCELL s 1 0 1 0 data_outa2~1
- 6 - C 20 LCELL s 1 0 1 0 data_outa3~1
- 6 - C 02 LCELL s 1 0 1 0 data_outa4~1
- 2 - C 04 LCELL s 1 0 1 0 data_outa5~1
- 4 - B 17 LCELL s 1 0 1 0 data_outa6~1
- 7 - B 11 LCELL s 1 0 1 0 data_outa7~1
- 5 - A 16 LCELL s 1 0 1 0 data_outb0~1
- 6 - A 07 LCELL s 1 0 1 0 data_outb1~1
- 5 - B 12 LCELL s 1 0 1 0 data_outb2~1
- 2 - C 20 LCELL s 1 0 1 0 data_outb3~1
- 8 - C 02 LCELL s 1 0 1 0 data_outb4~1
- 5 - C 04 LCELL s 1 0 1 0 data_outb5~1
- 3 - B 17 LCELL s 1 0 1 0 data_outb6~1
- 1 - B 11 LCELL s 1 0 1 0 data_outb7~1
- 7 - C 01 LCELL s 1 0 1 0 rama_oe~1
- 6 - B 14 LCELL s 1 0 1 0 ramb_oe~1
- 8 - C 17 OR2 3 0 1 0 :168
- 4 - B 23 OR2 3 0 1 0 :171
- 6 - B 13 OR2 3 0 1 0 :174
- 2 - B 08 OR2 3 0 1 0 :177
- 7 - A 02 OR2 3 0 1 0 :180
- 2 - C 08 OR2 3 0 1 0 :183
- 4 - C 01 OR2 3 0 1 0 :186
- 1 - A 20 OR2 3 0 1 0 :189
- 6 - B 18 OR2 3 0 1 0 :192
- 1 - A 04 OR2 3 0 1 0 :195
- 5 - A 21 OR2 3 0 1 0 :198
- 3 - A 23 OR2 3 0 1 0 :201
- 2 - B 04 OR2 3 0 1 0 :204
- 2 - C 14 OR2 2 0 1 0 :206
- 4 - C 17 OR2 3 0 1 0 :209
- 2 - B 23 OR2 3 0 1 0 :212
- 1 - B 13 OR2 3 0 1 0 :215
- 8 - B 08 OR2 3 0 1 0 :218
- 1 - A 02 OR2 3 0 1 0 :221
- 8 - C 08 OR2 3 0 1 0 :224
- 1 - C 01 OR2 3 0 1 0 :227
- 2 - A 20 OR2 3 0 1 0 :230
- 8 - B 18 OR2 3 0 1 0 :233
- 4 - A 04 OR2 3 0 1 0 :236
- 1 - A 21 OR2 3 0 1 0 :239
- 4 - A 23 OR2 3 0 1 0 :242
- 4 - B 04 OR2 3 0 1 0 :245
- 4 - C 14 OR2 2 0 1 0 :248
- 6 - A 04 OR2 1 2 1 0 :259
- 8 - A 23 OR2 1 2 1 0 :262
- 3 - B 18 OR2 1 2 1 0 :265
- 1 - C 08 OR2 1 2 1 0 :268
- 6 - C 14 OR2 1 2 1 0 :271
- 3 - C 17 OR2 1 2 1 0 :274
- 7 - B 18 OR2 1 2 1 0 :277
- 2 - B 18 OR2 1 2 1 0 :280
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\hanpj\pld\dma\10k208\pingp.rpt
pingp
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 10/ 96( 10%) 8/ 48( 16%) 7/ 48( 14%) 5/16( 31%) 7/16( 43%) 4/16( 25%)
B: 8/ 96( 8%) 10/ 48( 20%) 14/ 48( 29%) 2/16( 12%) 8/16( 50%) 6/16( 37%)
C: 12/ 96( 12%) 8/ 48( 16%) 6/ 48( 12%) 5/16( 31%) 5/16( 31%) 6/16( 37%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 3/24( 12%) 1/4( 25%) 2/4( 50%) 0/4( 0%)
02: 3/24( 12%) 3/4( 75%) 0/4( 0%) 0/4( 0%)
03: 3/24( 12%) 0/4( 0%) 3/4( 75%) 0/4( 0%)
04: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
07: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
08: 3/24( 12%) 1/4( 25%) 2/4( 50%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
20: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
21: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
23: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
24: 3/24( 12%) 1/4( 25%) 2/4( 50%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\hanpj\pld\dma\10k208\pingp.rpt
pingp
** EQUATIONS **
dfv : INPUT;
ndfv : INPUT;
rd_addr0 : INPUT;
rd_addr1 : INPUT;
rd_addr2 : INPUT;
rd_addr3 : INPUT;
rd_addr4 : INPUT;
rd_addr5 : INPUT;
rd_addr6 : INPUT;
rd_addr7 : INPUT;
rd_addr8 : INPUT;
rd_addr9 : INPUT;
rd_addr10 : INPUT;
rd_addr11 : INPUT;
rd_addr12 : INPUT;
wr_addr0 : INPUT;
wr_addr1 : INPUT;
wr_addr2 : INPUT;
wr_addr3 : INPUT;
wr_addr4 : INPUT;
wr_addr5 : INPUT;
wr_addr6 : INPUT;
wr_addr7 : INPUT;
wr_addr8 : INPUT;
wr_addr9 : INPUT;
wr_addr10 : INPUT;
wr_addr11 : INPUT;
wr_addr12 : INPUT;
wr_clk : INPUT;
wr_data0 : INPUT;
wr_data1 : INPUT;
wr_data2 : INPUT;
wr_data3 : INPUT;
wr_data4 : INPUT;
wr_data5 : INPUT;
wr_data6 : INPUT;
wr_data7 : INPUT;
-- Node name is 'data_outa0~1' from file "pingp.tdf" line 23, column 11
-- Equation name is 'data_outa0~1', location is LC8_A16, type is buried.
-- synthesized logic cell
_LC8_A16 = LCELL( wr_data0);
-- Node name is 'data_outa1~1' from file "pingp.tdf" line 23, column 11
-- Equation name is 'data_outa1~1', location is LC1_A7, type is buried.
-- synthesized logic cell
_LC1_A7 = LCELL( wr_data1);
-- Node name is 'data_outa2~1' from file "pingp.tdf" line 23, column 11
-- Equation name is 'data_outa2~1', location is LC8_B12, type is buried.
-- synthesized logic cell
_LC8_B12 = LCELL( wr_data2);
-- Node name is 'data_outa3~1' from file "pingp.tdf" line 23, column 11
-- Equation name is 'data_outa3~1', location is LC6_C20, type is buried.
-- synthesized logic cell
_LC6_C20 = LCELL( wr_data3);
-- Node name is 'data_outa4~1' from file "pingp.tdf" line 23, column 11
-- Equation name is 'data_outa4~1', location is LC6_C2, type is buried.
-- synthesized logic cell
_LC6_C2 = LCELL( wr_data4);
-- Node name is 'data_outa5~1' from file "pingp.tdf" line 23, column 11
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