📄 pingp.rpt
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Project Information e:\hanpj\pld\dma\10k208\pingp.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 05/21/2003 17:54:27
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
Untitled
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
pingp EPF10K10QC208-3 37 38 16 0 0 % 54 9 %
User Pins: 37 38 16
Project Information e:\hanpj\pld\dma\10k208\pingp.rpt
** PROJECT COMPILATION MESSAGES **
Warning: Ignored unnecessary INPUT pin 'wr'
Warning: Ignored unnecessary INPUT pin 'sync'
Warning: Ignored unnecessary INPUT pin 'rd_clk'
Device-Specific Information: e:\hanpj\pld\dma\10k208\pingp.rpt
pingp
***** Logic for device 'pingp' compiled without errors.
Device: EPF10K10QC208-3
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
r r r r r r r
a a r a a a a a r
m m r r d w R m m R R R r m R R w R w w w R R R R R R R r m R R R w R R m R w r R d
a b d d _ r E b a E E E d b E E r r r E r r r E E E E E E E d b E E E r E E a E r d E _
_ _ _ _ a _ S _ _ S S S _ _ S S _ a a S G _ _ _ V S S S S S S S _ _ S S S _ S S _ S _ _ S a
a a d a d a E G a a E E E a V a E E a m G m E N d d d C E E V E E E E E a G a E E E a V E E a E d a E d
d d a d d d R N d d R R R d C d R R d b N a R D a a a C R R C R R R R R d N d R R R d C R R d R a d R d
d d t d r d V D d d V V V d C d V V d _ D _ V I t t t I V V C V V V V V d D d V V V d C V V d V t d V r
r r a r 1 r E I r r E E E r I r E E r o I w E N a a a N E E I E E E E E r I r E E E r I E E r E a r E 1
1 1 1 0 0 7 D O 7 7 D D D 2 O 0 D D 8 e O r D T 1 3 0 T D D O D D D D D 5 O 5 D D D 9 O D D 9 D 7 9 D 2
----------------------------------------------------------------------------------------------------------_
/ 208 206 204 202 200 198 196 194 192 190 188 186 184 182 180 178 176 174 172 170 168 166 164 162 160 158 |_
/ 207 205 203 201 199 197 195 193 191 189 187 185 183 181 179 177 175 173 171 169 167 165 163 161 159 157 |
#TCK | 1 156 | ^DATA0
^CONF_DONE | 2 155 | ^DCLK
^nCEO | 3 154 | ^nCE
#TDO | 4 153 | #TDI
VCCIO | 5 152 | GNDIO
VCCINT | 6 151 | GNDINT
N.C. | 7 150 | rama_data1
N.C. | 8 149 | ramb_addr4
N.C. | 9 148 | wr_addr10
ramb_addr10 | 10 147 | ramb_addr9
rd_addr4 | 11 146 | VCCIO
rama_addr11 | 12 145 | VCCINT
ramb_addr11 | 13 144 | rd_addr7
N.C. | 14 143 | ramb_data1
N.C. | 15 142 | rd_addr11
rama_addr10 | 16 141 | rama_addr4
ramb_data0 | 17 140 | N.C.
wr_addr11 | 18 139 | N.C.
rama_data0 | 19 138 | VCCIO
GNDIO | 20 137 | VCCINT
GNDINT | 21 136 | ramb_data7
VCCIO | 22 135 | wr_addr12
VCCINT | 23 134 | wr_addr2
ramb_addr2 | 24 133 | ramb_addr12
rd_data7 | 25 132 | rama_data2
ramb_data6 | 26 131 | ramb_data2
rama_data6 | 27 EPF10K10QC208-3 130 | GNDIO
ramb_addr8 | 28 129 | GNDINT
rama_addr2 | 29 128 | rama_data7
rama_addr8 | 30 127 | ramb_addr3
rd_data6 | 31 126 | N.C.
GNDIO | 32 125 | N.C.
GNDINT | 33 124 | GNDIO
VCCIO | 34 123 | GNDINT
VCCINT | 35 122 | rd_data3
N.C. | 36 121 | rama_data5
N.C. | 37 120 | wr_addr6
wr_data4 | 38 119 | wr_addr0
ramb_data3 | 39 118 | VCCIO
rd_data5 | 40 117 | VCCINT
ramb_wr | 41 116 | ramb_data5
VCCIO | 42 115 | rama_data4
VCCINT | 43 114 | N.C.
rd_addr6 | 44 113 | N.C.
rama_data3 | 45 112 | rama_oe
wr_clk | 46 111 | ramb_data4
rama_addr0 | 47 110 | VCCIO
GNDIO | 48 109 | VCCINT
GNDINT | 49 108 | ^MSEL0
#TMS | 50 107 | ^MSEL1
#TRST | 51 106 | VCCINT
^nSTATUS | 52 105 | ^nCONFIG
| 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 _|
\ 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 |
\-----------------------------------------------------------------------------------------------------------
R w R R R R G r R r w r R V R R R R R G R r R V V n w d G G R V R R w R R R G r r r w R R V w r r w r r
E r E E E E N d E d r d E C E E E E E N E d E C C d r f N N E C E E r E E E N a d a r E E C r d a r a a
S _ S S S S D _ S _ _ _ S C S S S S S D S _ S C C f _ v D D S C S S _ S S S D m _ m _ S S C _ _ m _ m m
E a E E E E I a E a d d E I E E E E E I E d E I I v d I I E I E E a E E E I a a a d E E I a d a a a b
R d R R R R O d R d a a R O R R R R R O R a R N N a N N R O R R d R R R O _ d _ a R R O d a _ d _ _
V d V V V V d V d t t V V V V V V V t V T T t T T V V V d V V V a d a t V V d t a d a a
E r E E E E r E r a a E E E E E E E a E a E E E r E E E d r d a E E r a d r d d
D 1 D D D D 8 D 1 6 2 D D D D D D D 4 D 2 D D D 3 D D D d 3 d 5 D D 4 0 d 5 d d
r r r r r
5 3 1 6 6
2
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: e:\hanpj\pld\dma\10k208\pingp.rpt
pingp
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A2 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 3/22( 13%)
A4 3/ 8( 37%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 5/22( 22%)
A7 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 1/22( 4%)
A16 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 1/22( 4%)
A20 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
A21 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 3/22( 13%)
A23 3/ 8( 37%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 5/22( 22%)
B4 2/ 8( 25%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
B8 2/ 8( 25%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
B11 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 1/22( 4%)
B12 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 1/22( 4%)
B13 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 3/22( 13%)
B14 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%)
B17 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 1/22( 4%)
B18 5/ 8( 62%) 1/ 8( 12%) 4/ 8( 50%) 0/2 0/2 9/22( 40%)
B23 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
C1 3/ 8( 37%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
C2 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 1/22( 4%)
C4 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 1/22( 4%)
C8 3/ 8( 37%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 5/22( 22%)
C14 3/ 8( 37%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
C17 3/ 8( 37%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 5/22( 22%)
C20 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 1/22( 4%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 85/128 ( 66%)
Total logic cells used: 54/576 ( 9%)
Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 2.29/4 ( 57%)
Total fan-in: 124/2304 ( 5%)
Total input pins required: 37
Total input I/O cell registers required: 0
Total output pins required: 38
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 16
Total reserved pins required 0
Total logic cells required: 54
Total flipflops required: 0
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 18/ 576 ( 3%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 2 0 3 0 0 2 0 0 0 0 0 0 0 0 0 2 0 0 0 2 2 0 3 0 16/0
B: 0 0 0 2 0 0 0 2 0 0 2 2 0 2 1 0 0 2 5 0 0 0 0 2 0 20/0
C: 3 2 0 2 0 0 0 3 0 0 0 0 0 0 3 0 0 3 0 0 2 0 0 0 0 18/0
Total: 3 4 0 7 0 0 2 5 0 0 2 2 0 2 4 0 2 5 5 0 4 2 0 5 0 54/0
Device-Specific Information: e:\hanpj\pld\dma\10k208\pingp.rpt
pingp
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
80 - - - -- INPUT G 0 0 0 37 dfv
78 - - - -- INPUT G 0 0 0 1 ndfv
19 - - A -- BIDIR 0 1 0 1 rama_data0
150 - - A -- BIDIR 0 1 0 1 rama_data1
132 - - B -- BIDIR 0 1 0 1 rama_data2
45 - - C -- BIDIR 0 1 0 1 rama_data3
115 - - C -- BIDIR 0 1 0 1 rama_data4
121 - - C -- BIDIR 0 1 0 1 rama_data5
27 - - B -- BIDIR 0 1 0 1 rama_data6
128 - - B -- BIDIR 0 1 0 1 rama_data7
17 - - A -- BIDIR 0 1 0 1 ramb_data0
143 - - A -- BIDIR 0 1 0 1 ramb_data1
131 - - B -- BIDIR 0 1 0 1 ramb_data2
39 - - C -- BIDIR 0 1 0 1 ramb_data3
111 - - C -- BIDIR 0 1 0 1 ramb_data4
116 - - C -- BIDIR 0 1 0 1 ramb_data5
26 - - B -- BIDIR 0 1 0 1 ramb_data6
136 - - B -- BIDIR 0 1 0 1 ramb_data7
205 - - - 23 INPUT 0 0 0 2 rd_addr0
62 - - - 19 INPUT 0 0 0 2 rd_addr1
195 - - - 17 INPUT 0 0 0 2 rd_addr2
93 - - - 07 INPUT 0 0 0 2 rd_addr3
11 - - A -- INPUT 0 0 0 2 rd_addr4
172 - - - 08 INPUT 0 0 0 2 rd_addr5
44 - - C -- INPUT 0 0 0 2 rd_addr6
144 - - A -- INPUT 0 0 0 2 rd_addr7
60 - - - 21 INPUT 0 0 0 2 rd_addr8
159 - - - 02 INPUT 0 0 0 2 rd_addr9
204 - - - 22 INPUT 0 0 0 2 rd_addr10
142 - - A -- INPUT 0 0 0 2 rd_addr11
157 - - - 01 INPUT 0 0 0 2 rd_addr12
119 - - C -- INPUT 0 0 0 2 wr_addr0
54 - - - 24 INPUT 0 0 0 2 wr_addr1
134 - - B -- INPUT 0 0 0 2 wr_addr2
87 - - - 10 INPUT 0 0 0 2 wr_addr3
99 - - - 04 INPUT 0 0 0 2 wr_addr4
102 - - - 02 INPUT 0 0 0 2 wr_addr5
120 - - C -- INPUT 0 0 0 2 wr_addr6
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