nvsram.rpt

这是用AHDL语言编写的一个PCI采集系统的逻辑源码

  _EQ020 = !RD_ADDRESS11
         #  RD_ADDRESS10
         # !RD_ADDRESS9
         #  RD_ADDRESS8;

-- Node name is '~146~4' from file "nvsram.tdf" line 24, column 18
-- Equation name is '~146~4', location is LC8_B3, type is buried.
-- synthesized logic cell 
_LC8_B3  = LCELL( _EQ021);
  _EQ021 = !RD_ADDRESS15
         # !RD_ADDRESS14
         # !RD_ADDRESS13
         #  RD_ADDRESS12;

-- Node name is '~146~5' from file "nvsram.tdf" line 24, column 18
-- Equation name is '~146~5', location is LC3_B6, type is buried.
-- synthesized logic cell 
_LC3_B6  = LCELL( _EQ022);
  _EQ022 =  RD_ADDRESS7
         #  _LC6_B5
         #  _LC5_B6
         #  _LC8_B3;

-- Node name is ':146' from file "nvsram.tdf" line 24, column 18
-- Equation name is '_LC8_B9', type is buried 
_LC8_B9  = LCELL( _EQ023);
  _EQ023 =  RD_ADDRESS0
         #  RD_ADDRESS3
         #  _LC6_B9
         #  _LC3_B6;

-- Node name is ':153' from file "nvsram.tdf" line 27, column 31
-- Equation name is '_LC7_B9', type is buried 
_LC7_B9  = LCELL( _EQ024);
  _EQ024 =  RD_ADDRESS0 &  RD_ADDRESS1;

-- Node name is ':161' from file "nvsram.tdf" line 27, column 31
-- Equation name is '_LC2_B9', type is buried 
_LC2_B9  = LCELL( _EQ025);
  _EQ025 =  RD_ADDRESS0 &  RD_ADDRESS1 &  RD_ADDRESS2 &  RD_ADDRESS3;

-- Node name is ':165' from file "nvsram.tdf" line 27, column 31
-- Equation name is '_LC5_B5', type is buried 
_LC5_B5  = LCELL( _EQ026);
  _EQ026 =  _LC2_B9 &  RD_ADDRESS4;

-- Node name is ':173' from file "nvsram.tdf" line 27, column 31
-- Equation name is '_LC2_B5', type is buried 
_LC2_B5  = LCELL( _EQ027);
  _EQ027 =  _LC2_B9 &  RD_ADDRESS4 &  RD_ADDRESS5 &  RD_ADDRESS6;

-- Node name is ':177' from file "nvsram.tdf" line 27, column 31
-- Equation name is '_LC7_B6', type is buried 
_LC7_B6  = LCELL( _EQ028);
  _EQ028 =  _LC2_B5 &  RD_ADDRESS7;

-- Node name is ':185' from file "nvsram.tdf" line 27, column 31
-- Equation name is '_LC4_B6', type is buried 
_LC4_B6  = LCELL( _EQ029);
  _EQ029 =  _LC2_B5 &  RD_ADDRESS7 &  RD_ADDRESS8 &  RD_ADDRESS9;

-- Node name is ':189' from file "nvsram.tdf" line 27, column 31
-- Equation name is '_LC7_B2', type is buried 
_LC7_B2  = LCELL( _EQ030);
  _EQ030 =  _LC4_B6 &  RD_ADDRESS10;

-- Node name is ':197' from file "nvsram.tdf" line 27, column 31
-- Equation name is '_LC3_B2', type is buried 
_LC3_B2  = LCELL( _EQ031);
  _EQ031 =  _LC4_B6 &  RD_ADDRESS10 &  RD_ADDRESS11 &  RD_ADDRESS12;

-- Node name is ':205' from file "nvsram.tdf" line 27, column 31
-- Equation name is '_LC5_B3', type is buried 
_LC5_B3  = LCELL( _EQ032);
  _EQ032 =  _LC3_B2 &  RD_ADDRESS13 &  RD_ADDRESS14;

-- Node name is ':250' from file "nvsram.tdf" line 36, column 9
-- Equation name is '_LC8_B4', type is buried 
_LC8_B4  = LCELL( _EQ033);
  _EQ033 = !NVSRAM_WRITE_OE &  RD_ADDRESS0
         #  NVSRAM_WRITE_OE &  WR_ADDRESS0;

-- Node name is ':253' from file "nvsram.tdf" line 36, column 9
-- Equation name is '_LC4_B4', type is buried 
_LC4_B4  = LCELL( _EQ034);
  _EQ034 = !NVSRAM_WRITE_OE &  RD_ADDRESS1
         #  NVSRAM_WRITE_OE &  WR_ADDRESS1;

-- Node name is ':256' from file "nvsram.tdf" line 36, column 9
-- Equation name is '_LC1_B4', type is buried 
_LC1_B4  = LCELL( _EQ035);
  _EQ035 = !NVSRAM_WRITE_OE &  RD_ADDRESS2
         #  NVSRAM_WRITE_OE &  WR_ADDRESS2;

-- Node name is ':259' from file "nvsram.tdf" line 36, column 9
-- Equation name is '_LC6_B4', type is buried 
_LC6_B4  = LCELL( _EQ036);
  _EQ036 = !NVSRAM_WRITE_OE &  RD_ADDRESS3
         #  NVSRAM_WRITE_OE &  WR_ADDRESS3;

-- Node name is ':262' from file "nvsram.tdf" line 36, column 9
-- Equation name is '_LC8_B5', type is buried 
_LC8_B5  = LCELL( _EQ037);
  _EQ037 = !NVSRAM_WRITE_OE &  RD_ADDRESS4
         #  NVSRAM_WRITE_OE &  WR_ADDRESS4;

-- Node name is ':265' from file "nvsram.tdf" line 36, column 9
-- Equation name is '_LC7_B5', type is buried 
_LC7_B5  = LCELL( _EQ038);
  _EQ038 = !NVSRAM_WRITE_OE &  RD_ADDRESS5
         #  NVSRAM_WRITE_OE &  WR_ADDRESS5;

-- Node name is ':268' from file "nvsram.tdf" line 36, column 9
-- Equation name is '_LC3_B4', type is buried 
_LC3_B4  = LCELL( _EQ039);
  _EQ039 = !NVSRAM_WRITE_OE &  RD_ADDRESS6
         #  NVSRAM_WRITE_OE &  WR_ADDRESS6;

-- Node name is ':271' from file "nvsram.tdf" line 36, column 9
-- Equation name is '_LC2_B6', type is buried 
_LC2_B6  = LCELL( _EQ040);
  _EQ040 = !NVSRAM_WRITE_OE &  RD_ADDRESS7
         #  NVSRAM_WRITE_OE &  WR_ADDRESS7;

-- Node name is ':274' from file "nvsram.tdf" line 36, column 9
-- Equation name is '_LC5_B4', type is buried 
_LC5_B4  = LCELL( _EQ041);
  _EQ041 = !NVSRAM_WRITE_OE &  RD_ADDRESS8
         #  NVSRAM_WRITE_OE &  WR_ADDRESS8;

-- Node name is ':277' from file "nvsram.tdf" line 36, column 9
-- Equation name is '_LC7_B4', type is buried 
_LC7_B4  = LCELL( _EQ042);
  _EQ042 = !NVSRAM_WRITE_OE &  RD_ADDRESS9
         #  NVSRAM_WRITE_OE &  WR_ADDRESS9;

-- Node name is ':280' from file "nvsram.tdf" line 36, column 9
-- Equation name is '_LC2_B2', type is buried 
_LC2_B2  = LCELL( _EQ043);
  _EQ043 = !NVSRAM_WRITE_OE &  RD_ADDRESS10
         #  NVSRAM_WRITE_OE &  WR_ADDRESS10;

-- Node name is ':283' from file "nvsram.tdf" line 36, column 9
-- Equation name is '_LC6_B2', type is buried 
_LC6_B2  = LCELL( _EQ044);
  _EQ044 = !NVSRAM_WRITE_OE &  RD_ADDRESS11
         #  NVSRAM_WRITE_OE &  WR_ADDRESS11;

-- Node name is ':286' from file "nvsram.tdf" line 36, column 9
-- Equation name is '_LC1_B2', type is buried 
_LC1_B2  = LCELL( _EQ045);
  _EQ045 = !NVSRAM_WRITE_OE &  RD_ADDRESS12
         #  NVSRAM_WRITE_OE &  WR_ADDRESS12;

-- Node name is ':289' from file "nvsram.tdf" line 36, column 9
-- Equation name is '_LC2_B3', type is buried 
_LC2_B3  = LCELL( _EQ046);
  _EQ046 = !NVSRAM_WRITE_OE &  RD_ADDRESS13
         #  NVSRAM_WRITE_OE &  WR_ADDRESS13;

-- Node name is ':292' from file "nvsram.tdf" line 36, column 9
-- Equation name is '_LC7_C3', type is buried 
_LC7_C3  = LCELL( _EQ047);
  _EQ047 = !NVSRAM_WRITE_OE &  RD_ADDRESS14
         #  NVSRAM_WRITE_OE &  WR_ADDRESS14;

-- Node name is ':295' from file "nvsram.tdf" line 36, column 9
-- Equation name is '_LC1_B3', type is buried 
_LC1_B3  = LCELL( _EQ048);
  _EQ048 = !NVSRAM_WRITE_OE &  RD_ADDRESS15
         #  NVSRAM_WRITE_OE &  WR_ADDRESS15;

-- Node name is ':298' from file "nvsram.tdf" line 36, column 9
-- Equation name is '_LC2_B4', type is buried 
_LC2_B4  = LCELL( _EQ049);
  _EQ049 = !NVSRAM_WRITE_OE &  RD_ADDRESS16
         #  NVSRAM_WRITE_OE &  WR_ADDRESS16;



Project Information                         e:\hanpj\pld\dma\10k208\nvsram.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = off
      Automatic Global Preset             = off
      Automatic Global Output Enable      = off
      Automatic Fast I/O                  = on
      Automatic Register Packing          = on
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = on
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:01
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:04


Memory Allocated
-----------------

Peak memory allocated during compilation  = 21,542K