📄 nvsram.rpt
字号:
40 - - C -- INPUT 0 0 0 1 TM_WR/
172 - - - 08 INPUT 0 0 0 1 WR_ADDRESS0
28 - - B -- INPUT 0 0 0 1 WR_ADDRESS1
166 - - - 05 INPUT 0 0 0 1 WR_ADDRESS2
97 - - - 05 INPUT 0 0 0 1 WR_ADDRESS3
25 - - B -- INPUT 0 0 0 1 WR_ADDRESS4
29 - - B -- INPUT 0 0 0 1 WR_ADDRESS5
93 - - - 07 INPUT 0 0 0 1 WR_ADDRESS6
159 - - - 02 INPUT 0 0 0 1 WR_ADDRESS7
31 - - B -- INPUT 0 0 0 1 WR_ADDRESS8
85 - - - 11 INPUT 0 0 0 1 WR_ADDRESS9
90 - - - 08 INPUT 0 0 0 1 WR_ADDRESS10
27 - - B -- INPUT 0 0 0 1 WR_ADDRESS11
24 - - B -- INPUT 0 0 0 1 WR_ADDRESS12
30 - - B -- INPUT 0 0 0 1 WR_ADDRESS13
47 - - C -- INPUT 0 0 0 1 WR_ADDRESS14
92 - - - 08 INPUT 0 0 0 1 WR_ADDRESS15
26 - - B -- INPUT 0 0 0 1 WR_ADDRESS16
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\hanpj\pld\dma\10k208\nvsram.rpt
nvsram
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
101 - - - 03 OUTPUT 0 1 0 0 TMA0
133 - - B -- OUTPUT 0 1 0 0 TMA1
163 - - - 04 OUTPUT 0 1 0 0 TMA2
131 - - B -- OUTPUT 0 1 0 0 TMA3
127 - - B -- OUTPUT 0 1 0 0 TMA4
95 - - - 06 OUTPUT 0 1 0 0 TMA5
134 - - B -- OUTPUT 0 1 0 0 TMA6
96 - - - 05 OUTPUT 0 1 0 0 TMA7
132 - - B -- OUTPUT 0 1 0 0 TMA8
164 - - - 04 OUTPUT 0 1 0 0 TMA9
157 - - - 01 OUTPUT 0 1 0 0 TMA10
128 - - B -- OUTPUT 0 1 0 0 TMA11
136 - - B -- OUTPUT 0 1 0 0 TMA12
135 - - B -- OUTPUT 0 1 0 0 TMA13
112 - - C -- OUTPUT 0 1 0 0 TMA14
100 - - - 03 OUTPUT 0 1 0 0 TMA15
161 - - - 03 OUTPUT 0 1 0 0 TMA16
111 - - C -- TRI 0 1 0 0 TMD0
13 - - A -- TRI 0 1 0 0 TMD1
121 - - C -- TRI 0 1 0 0 TMD2
16 - - A -- TRI 0 1 0 0 TMD3
17 - - A -- TRI 0 1 0 0 TMD4
39 - - C -- TRI 0 1 0 0 TMD5
12 - - A -- TRI 0 1 0 0 TMD6
38 - - C -- TRI 0 1 0 0 TMD7
119 - - C -- OUTPUT 0 1 0 0 TM_OE/
120 - - C -- OUTPUT 0 1 0 0 TM_WE/
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\hanpj\pld\dma\10k208\nvsram.rpt
nvsram
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 4 - B 09 DFFE + 1 1 0 6 RD_ADDRESS0
- 3 - B 09 DFFE + 1 2 0 5 RD_ADDRESS1
- 1 - B 09 DFFE + 1 3 0 4 RD_ADDRESS2
- 5 - B 09 DFFE + 1 3 0 3 RD_ADDRESS3
- 1 - B 05 DFFE + 1 2 0 5 RD_ADDRESS4
- 3 - B 05 DFFE + 1 3 0 4 RD_ADDRESS5
- 4 - B 05 DFFE + 1 3 0 3 RD_ADDRESS6
- 6 - B 06 DFFE + 1 2 0 5 RD_ADDRESS7
- 1 - B 06 DFFE + 1 3 0 4 RD_ADDRESS8
- 8 - B 06 DFFE + 1 3 0 3 RD_ADDRESS9
- 5 - B 02 DFFE + 1 2 0 5 RD_ADDRESS10
- 8 - B 02 DFFE + 1 3 0 4 RD_ADDRESS11
- 4 - B 02 DFFE + 1 3 0 3 RD_ADDRESS12
- 3 - B 03 DFFE + 1 2 0 4 RD_ADDRESS13
- 4 - B 03 DFFE + 1 3 0 3 RD_ADDRESS14
- 6 - B 03 DFFE + 1 2 0 3 RD_ADDRESS15
- 7 - B 03 DFFE + 1 3 0 2 RD_ADDRESS16
- 8 - C 07 LCELL s 1 0 1 0 TEMP_DATA0~1
- 4 - A 23 LCELL s 1 0 1 0 TEMP_DATA1~1
- 2 - C 06 LCELL s 1 0 1 0 TEMP_DATA2~1
- 5 - A 19 LCELL s 1 0 1 0 TEMP_DATA3~1
- 5 - A 16 LCELL s 1 0 1 0 TEMP_DATA4~1
- 1 - C 18 LCELL s 1 0 1 0 TEMP_DATA5~1
- 3 - A 15 LCELL s 1 0 1 0 TEMP_DATA6~1
- 1 - C 14 LCELL s 1 0 1 0 TEMP_DATA7~1
- 4 - C 03 LCELL s 1 0 1 0 TM_OE/~1
- 2 - C 12 LCELL s 1 0 1 0 TM_WE/~1
- 6 - B 09 OR2 s 0 3 0 1 ~146~1
- 6 - B 05 OR2 s 0 3 0 1 ~146~2
- 5 - B 06 OR2 s 0 4 0 1 ~146~3
- 8 - B 03 OR2 s 0 4 0 1 ~146~4
- 3 - B 06 OR2 s 0 4 0 1 ~146~5
- 8 - B 09 OR2 0 4 0 17 :146
- 7 - B 09 AND2 0 2 0 1 :153
- 2 - B 09 AND2 0 4 0 4 :161
- 5 - B 05 AND2 0 2 0 1 :165
- 2 - B 05 AND2 0 4 0 4 :173
- 7 - B 06 AND2 0 2 0 1 :177
- 4 - B 06 AND2 0 4 0 4 :185
- 7 - B 02 AND2 0 2 0 1 :189
- 3 - B 02 AND2 0 4 0 3 :197
- 5 - B 03 AND2 0 3 0 2 :205
- 8 - B 04 OR2 2 1 1 0 :250
- 4 - B 04 OR2 2 1 1 0 :253
- 1 - B 04 OR2 2 1 1 0 :256
- 6 - B 04 OR2 2 1 1 0 :259
- 8 - B 05 OR2 2 1 1 0 :262
- 7 - B 05 OR2 2 1 1 0 :265
- 3 - B 04 OR2 2 1 1 0 :268
- 2 - B 06 OR2 2 1 1 0 :271
- 5 - B 04 OR2 2 1 1 0 :274
- 7 - B 04 OR2 2 1 1 0 :277
- 2 - B 02 OR2 2 1 1 0 :280
- 6 - B 02 OR2 2 1 1 0 :283
- 1 - B 02 OR2 2 1 1 0 :286
- 2 - B 03 OR2 2 1 1 0 :289
- 7 - C 03 OR2 2 1 1 0 :292
- 1 - B 03 OR2 2 1 1 0 :295
- 2 - B 04 OR2 2 1 1 0 :298
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\hanpj\pld\dma\10k208\nvsram.rpt
nvsram
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 3/ 96( 3%) 0/ 48( 0%) 2/ 48( 4%) 1/16( 6%) 0/16( 0%) 4/16( 25%)
B: 15/ 96( 15%) 29/ 48( 60%) 0/ 48( 0%) 8/16( 50%) 8/16( 50%) 0/16( 0%)
C: 8/ 96( 8%) 3/ 48( 6%) 2/ 48( 4%) 4/16( 25%) 3/16( 18%) 4/16( 25%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
02: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
03: 4/24( 16%) 0/4( 0%) 3/4( 75%) 0/4( 0%)
04: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
05: 3/24( 12%) 2/4( 50%) 1/4( 25%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
08: 3/24( 12%) 3/4( 75%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\hanpj\pld\dma\10k208\nvsram.rpt
nvsram
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 17 SRC_CLK
Device-Specific Information: e:\hanpj\pld\dma\10k208\nvsram.rpt
nvsram
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 43 NVSRAM_WRITE_OE
Device-Specific Information: e:\hanpj\pld\dma\10k208\nvsram.rpt
nvsram
** EQUATIONS **
DATA0 : INPUT;
DATA1 : INPUT;
DATA2 : INPUT;
DATA3 : INPUT;
DATA4 : INPUT;
DATA5 : INPUT;
DATA6 : INPUT;
DATA7 : INPUT;
NVSRAM_WRITE_OE : INPUT;
SRC_CLK : INPUT;
TM_WR/ : INPUT;
WR_ADDRESS0 : INPUT;
WR_ADDRESS1 : INPUT;
WR_ADDRESS2 : INPUT;
WR_ADDRESS3 : INPUT;
WR_ADDRESS4 : INPUT;
WR_ADDRESS5 : INPUT;
WR_ADDRESS6 : INPUT;
WR_ADDRESS7 : INPUT;
WR_ADDRESS8 : INPUT;
WR_ADDRESS9 : INPUT;
WR_ADDRESS10 : INPUT;
WR_ADDRESS11 : INPUT;
WR_ADDRESS12 : INPUT;
WR_ADDRESS13 : INPUT;
WR_ADDRESS14 : INPUT;
WR_ADDRESS15 : INPUT;
WR_ADDRESS16 : INPUT;
-- Node name is 'RD_ADDRESS0' from file "nvsram.tdf" line 16, column 13
-- Equation name is 'RD_ADDRESS0', location is LC4_B9, type is buried.
RD_ADDRESS0 = DFFE( _EQ001, GLOBAL( SRC_CLK), !NVSRAM_WRITE_OE, VCC, VCC);
_EQ001 = _LC8_B9 & !RD_ADDRESS0;
-- Node name is 'RD_ADDRESS1' from file "nvsram.tdf" line 16, column 13
-- Equation name is 'RD_ADDRESS1', location is LC3_B9, type is buried.
RD_ADDRESS1 = DFFE( _EQ002, GLOBAL( SRC_CLK), !NVSRAM_WRITE_OE, VCC, VCC);
_EQ002 = _LC8_B9 & !RD_ADDRESS0 & RD_ADDRESS1
# _LC8_B9 & RD_ADDRESS0 & !RD_ADDRESS1;
-- Node name is 'RD_ADDRESS2' from file "nvsram.tdf" line 16, column 13
-- Equation name is 'RD_ADDRESS2', location is LC1_B9, type is buried.
RD_ADDRESS2 = DFFE( _EQ003, GLOBAL( SRC_CLK), !NVSRAM_WRITE_OE, VCC, VCC);
_EQ003 = _LC8_B9 & !RD_ADDRESS1 & RD_ADDRESS2
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -