comp.map.eqn

一个比较器的实现方法

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-- programming logic devices manufactured by Altera and sold by 
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-- applicable agreement for further details.
--A1L5Q is fig_sad_min~reg0
--operation mode is normal

A1L5Q_lut_out = comp_ready & !A1L72;
A1L5Q = DFFEA(A1L5Q_lut_out, clk, , , st_mv_sel, , );

--A1L4Q is fig_sad_min~19
--operation mode is normal

A1L4Q = A1L5Q;


--A1L67Q is reg_sad[0]~reg0
--operation mode is normal

A1L67Q_lut_out = reg_r1[0];
A1L67Q = DFFEA(A1L67Q_lut_out, clk, , , st_mv_table, , );

--A1L57Q is reg_sad[0]~11
--operation mode is normal

A1L57Q = A1L67Q;


--A1L97Q is reg_sad[1]~reg0
--operation mode is normal

A1L97Q_lut_out = reg_r1[1];
A1L97Q = DFFEA(A1L97Q_lut_out, clk, , , st_mv_table, , );

--A1L87Q is reg_sad[1]~12
--operation mode is normal

A1L87Q = A1L97Q;


--A1L28Q is reg_sad[2]~reg0
--operation mode is normal

A1L28Q_lut_out = reg_r1[2];
A1L28Q = DFFEA(A1L28Q_lut_out, clk, , , st_mv_table, , );

--A1L18Q is reg_sad[2]~13
--operation mode is normal

A1L18Q = A1L28Q;


--A1L58Q is reg_sad[3]~reg0
--operation mode is normal

A1L58Q_lut_out = reg_r1[3];
A1L58Q = DFFEA(A1L58Q_lut_out, clk, , , st_mv_table, , );

--A1L48Q is reg_sad[3]~14
--operation mode is normal

A1L48Q = A1L58Q;


--A1L88Q is reg_sad[4]~reg0
--operation mode is normal

A1L88Q_lut_out = reg_r1[4];
A1L88Q = DFFEA(A1L88Q_lut_out, clk, , , st_mv_table, , );

--A1L78Q is reg_sad[4]~15
--operation mode is normal

A1L78Q = A1L88Q;


--A1L19Q is reg_sad[5]~reg0
--operation mode is normal

A1L19Q_lut_out = reg_r1[5];
A1L19Q = DFFEA(A1L19Q_lut_out, clk, , , st_mv_table, , );

--A1L09Q is reg_sad[5]~16
--operation mode is normal

A1L09Q = A1L19Q;


--A1L49Q is reg_sad[6]~reg0
--operation mode is normal

A1L49Q_lut_out = reg_r1[6];
A1L49Q = DFFEA(A1L49Q_lut_out, clk, , , st_mv_table, , );

--A1L39Q is reg_sad[6]~17
--operation mode is normal

A1L39Q = A1L49Q;


--A1L79Q is reg_sad[7]~reg0
--operation mode is normal

A1L79Q_lut_out = reg_r1[7];
A1L79Q = DFFEA(A1L79Q_lut_out, clk, , , st_mv_table, , );

--A1L69Q is reg_sad[7]~18
--operation mode is normal

A1L69Q = A1L79Q;


--A1L001Q is reg_sad[8]~reg0
--operation mode is normal

A1L001Q_lut_out = reg_r1[8];
A1L001Q = DFFEA(A1L001Q_lut_out, clk, , , st_mv_table, , );

--A1L99Q is reg_sad[8]~19
--operation mode is normal

A1L99Q = A1L001Q;


--A1L301Q is reg_sad[9]~reg0
--operation mode is normal

A1L301Q_lut_out = reg_r1[9];
A1L301Q = DFFEA(A1L301Q_lut_out, clk, , , st_mv_table, , );

--A1L201Q is reg_sad[9]~20
--operation mode is normal

A1L201Q = A1L301Q;


--A1L601Q is reg_sad[10]~reg0
--operation mode is normal

A1L601Q_lut_out = reg_r1[10];
A1L601Q = DFFEA(A1L601Q_lut_out, clk, , , st_mv_table, , );

--A1L501Q is reg_sad[10]~21
--operation mode is normal

A1L501Q = A1L601Q;


--reg_r1[0] is reg_r1[0]
--operation mode is normal

reg_r1[0]_lut_out = in_sad[0];
reg_r1[0] = DFFEA(reg_r1[0]_lut_out, clk, , , A1L07, , );

--A1L05Q is reg_r1[0]~76
--operation mode is normal

A1L05Q = reg_r1[0];


--reg_r1[1] is reg_r1[1]
--operation mode is normal

reg_r1[1]_lut_out = in_sad[1];
reg_r1[1] = DFFEA(reg_r1[1]_lut_out, clk, , , A1L07, , );

--A1L25Q is reg_r1[1]~77
--operation mode is normal

A1L25Q = reg_r1[1];


--reg_r1[2] is reg_r1[2]
--operation mode is normal

reg_r1[2]_lut_out = in_sad[2];
reg_r1[2] = DFFEA(reg_r1[2]_lut_out, clk, , , A1L07, , );

--A1L45Q is reg_r1[2]~78
--operation mode is normal

A1L45Q = reg_r1[2];


--reg_r1[3] is reg_r1[3]
--operation mode is normal

reg_r1[3]_lut_out = in_sad[3];
reg_r1[3] = DFFEA(reg_r1[3]_lut_out, clk, , , A1L07, , );

--A1L65Q is reg_r1[3]~79
--operation mode is normal

A1L65Q = reg_r1[3];


--reg_r1[4] is reg_r1[4]
--operation mode is normal

reg_r1[4]_lut_out = in_sad[4];
reg_r1[4] = DFFEA(reg_r1[4]_lut_out, clk, , , A1L07, , );

--A1L85Q is reg_r1[4]~80
--operation mode is normal

A1L85Q = reg_r1[4];


--reg_r1[5] is reg_r1[5]
--operation mode is normal

reg_r1[5]_lut_out = in_sad[5];
reg_r1[5] = DFFEA(reg_r1[5]_lut_out, clk, , , A1L07, , );

--A1L06Q is reg_r1[5]~81
--operation mode is normal

A1L06Q = reg_r1[5];


--reg_r1[6] is reg_r1[6]
--operation mode is normal

reg_r1[6]_lut_out = in_sad[6];
reg_r1[6] = DFFEA(reg_r1[6]_lut_out, clk, , , A1L07, , );

--A1L26Q is reg_r1[6]~82
--operation mode is normal

A1L26Q = reg_r1[6];


--reg_r1[7] is reg_r1[7]
--operation mode is normal

reg_r1[7]_lut_out = in_sad[7];
reg_r1[7] = DFFEA(reg_r1[7]_lut_out, clk, , , A1L07, , );

--A1L46Q is reg_r1[7]~83
--operation mode is normal

A1L46Q = reg_r1[7];


--reg_r1[8] is reg_r1[8]
--operation mode is normal

reg_r1[8]_lut_out = in_sad[8];
reg_r1[8] = DFFEA(reg_r1[8]_lut_out, clk, , , A1L07, , );

--A1L66Q is reg_r1[8]~84
--operation mode is normal

A1L66Q = reg_r1[8];


--reg_r1[9] is reg_r1[9]
--operation mode is normal

reg_r1[9]_lut_out = in_sad[9];
reg_r1[9] = DFFEA(reg_r1[9]_lut_out, clk, , , A1L07, , );

--A1L86Q is reg_r1[9]~85
--operation mode is normal

A1L86Q = reg_r1[9];


--reg_r1[10] is reg_r1[10]
--operation mode is normal

reg_r1[10]_lut_out = in_sad[10];
reg_r1[10] = DFFEA(reg_r1[10]_lut_out, clk, , , A1L07, , );

--A1L17Q is reg_r1[10]~86
--operation mode is normal

A1L17Q = reg_r1[10];


--A1L07 is reg_r1[10]~64
--operation mode is normal

A1L07 = st_mv_sel & (!A1L72 # !comp_ready);

--A1L27 is reg_r1[10]~87
--operation mode is normal

A1L27 = st_mv_sel & (!A1L72 # !comp_ready);


--A1L81 is LessThan~665
--operation mode is normal

A1L81 = reg_r1[10] & in_sad[10] & (reg_r1[9] $ !in_sad[9]) # !reg_r1[10] & !in_sad[10] & (reg_r1[9] $ !in_sad[9]);

--A1L13 is LessThan~698
--operation mode is normal

A1L13 = reg_r1[10] & in_sad[10] & (reg_r1[9] $ !in_sad[9]) # !reg_r1[10] & !in_sad[10] & (reg_r1[9] $ !in_sad[9]);


--A1L91 is LessThan~666
--operation mode is normal

A1L91 = reg_r1[10] & (reg_r1[9] & !in_sad[9] # !in_sad[10]) # !reg_r1[10] & reg_r1[9] & !in_sad[9] & !in_sad[10];

--A1L23 is LessThan~699
--operation mode is normal

A1L23 = reg_r1[10] & (reg_r1[9] & !in_sad[9] # !in_sad[10]) # !reg_r1[10] & reg_r1[9] & !in_sad[9] & !in_sad[10];


--A1L02 is LessThan~667
--operation mode is normal

A1L02 = !A1L91 & (in_sad[8] # !reg_r1[8] # !A1L81);

--A1L33 is LessThan~700
--operation mode is normal

A1L33 = !A1L91 & (in_sad[8] # !reg_r1[8] # !A1L81);

--A1L43 is LessThan~701
--operation mode is normal

A1L43 = !A1L91 & (in_sad[8] # !reg_r1[8] # !A1L81);


--A1L72 is LessThan~690
--operation mode is normal

A1L72 = (A1L82 # reg_r1[8] $ in_sad[8] # !A1L81) & CASCADE(A1L43);

--A1L53 is LessThan~702
--operation mode is normal

A1L53 = (A1L82 # reg_r1[8] $ in_sad[8] # !A1L81) & CASCADE(A1L43);


--A1L12 is LessThan~675
--operation mode is normal

A1L12 = reg_r1[3] & (reg_r1[2] & !in_sad[2] # !in_sad[3]) # !reg_r1[3] & reg_r1[2] & !in_sad[2] & !in_sad[3];

--A1L63 is LessThan~703
--operation mode is normal

A1L63 = reg_r1[3] & (reg_r1[2] & !in_sad[2] # !in_sad[3]) # !reg_r1[3] & reg_r1[2] & !in_sad[2] & !in_sad[3];


--A1L22 is LessThan~676
--operation mode is normal

A1L22 = A1L03 & (reg_r1[4] $ !in_sad[4]) # !A1L03 & A1L12 & (reg_r1[4] $ !in_sad[4]);

--A1L73 is LessThan~704
--operation mode is normal

A1L73 = A1L03 & (reg_r1[4] $ !in_sad[4]) # !A1L03 & A1L12 & (reg_r1[4] $ !in_sad[4]);


--A1L32 is LessThan~677
--operation mode is normal

A1L32 = reg_r1[7] & in_sad[7] & (reg_r1[6] $ !in_sad[6]) # !reg_r1[7] & !in_sad[7] & (reg_r1[6] $ !in_sad[6]);

--A1L83 is LessThan~705
--operation mode is normal

A1L83 = reg_r1[7] & in_sad[7] & (reg_r1[6] $ !in_sad[6]) # !reg_r1[7] & !in_sad[7] & (reg_r1[6] $ !in_sad[6]);


--A1L82 is LessThan~691
--operation mode is normal

A1L82 = (reg_r1[5] $ in_sad[5] # !A1L32 # !A1L22) & CASCADE(A1L44);

--A1L93 is LessThan~706
--operation mode is normal

A1L93 = (reg_r1[5] $ in_sad[5] # !A1L32 # !A1L22) & CASCADE(A1L44);


--A1L42 is LessThan~685
--operation mode is normal

A1L42 = in_sad[7] & (in_sad[6] # !reg_r1[7] # !reg_r1[6]) # !in_sad[7] & !reg_r1[7] & (in_sad[6] # !reg_r1[6]);

--A1L04 is LessThan~707
--operation mode is normal

A1L04 = in_sad[7] & (in_sad[6] # !reg_r1[7] # !reg_r1[6]) # !in_sad[7] & !reg_r1[7] & (in_sad[6] # !reg_r1[6]);

--A1L14 is LessThan~708
--operation mode is normal

A1L14 = in_sad[7] & (in_sad[6] # !reg_r1[7] # !reg_r1[6]) # !in_sad[7] & !reg_r1[7] & (in_sad[6] # !reg_r1[6]);


--A1L52 is LessThan~686
--operation mode is normal

A1L52 = reg_r1[4] & (!in_sad[4]);

--A1L24 is LessThan~709
--operation mode is normal

A1L24 = reg_r1[4] & (!in_sad[4]);


--A1L92 is LessThan~692
--operation mode is normal

A1L92 = (in_sad[5] & (!reg_r1[5] # !A1L52) # !in_sad[5] & !A1L52 & !reg_r1[5] # !A1L32) & CASCADE(A1L14);

--A1L34 is LessThan~710
--operation mode is normal

A1L34 = (in_sad[5] & (!reg_r1[5] # !A1L52) # !in_sad[5] & !A1L52 & !reg_r1[5] # !A1L32) & CASCADE(A1L14);

--A1L44 is LessThan~711
--operation mode is normal

A1L44 = (in_sad[5] & (!reg_r1[5] # !A1L52) # !in_sad[5] & !A1L52 & !reg_r1[5] # !A1L32) & CASCADE(A1L14);


--A1L62 is LessThan~688
--operation mode is normal

A1L62 = reg_r1[3] & in_sad[3] & (reg_r1[2] $ !in_sad[2]) # !reg_r1[3] & !in_sad[3] & (reg_r1[2] $ !in_sad[2]);

--A1L54 is LessThan~712
--operation mode is normal

A1L54 = reg_r1[3] & in_sad[3] & (reg_r1[2] $ !in_sad[2]) # !reg_r1[3] & !in_sad[3] & (reg_r1[2] $ !in_sad[2]);

--A1L64 is LessThan~713
--operation mode is normal

A1L64 = reg_r1[3] & in_sad[3] & (reg_r1[2] $ !in_sad[2]) # !reg_r1[3] & !in_sad[3] & (reg_r1[2] $ !in_sad[2]);


--A1L03 is LessThan~693
--operation mode is normal

A1L03 = (reg_r1[1] & (reg_r1[0] & !in_sad[0] # !in_sad[1]) # !reg_r1[1] & reg_r1[0] & !in_sad[0] & !in_sad[1]) & CASCADE(A1L64);

--A1L74 is LessThan~714
--operation mode is normal

A1L74 = (reg_r1[1] & (reg_r1[0] & !in_sad[0] # !in_sad[1]) # !reg_r1[1] & reg_r1[0] & !in_sad[0] & !in_sad[1]) & CASCADE(A1L64);


--comp_ready is comp_ready
--operation mode is input

comp_ready = INPUT();


--clk is clk
--operation mode is input

clk = INPUT();


--st_mv_table is st_mv_table
--operation mode is input

st_mv_table = INPUT();


--st_mv_sel is st_mv_sel
--operation mode is input

st_mv_sel = INPUT();


--in_sad[0] is in_sad[0]
--operation mode is input

in_sad[0] = INPUT();


--in_sad[1] is in_sad[1]
--operation mode is input

in_sad[1] = INPUT();


--in_sad[2] is in_sad[2]
--operation mode is input

in_sad[2] = INPUT();


--in_sad[3] is in_sad[3]
--operation mode is input

in_sad[3] = INPUT();


--in_sad[4] is in_sad[4]
--operation mode is input

in_sad[4] = INPUT();


--in_sad[5] is in_sad[5]
--operation mode is input

in_sad[5] = INPUT();


--in_sad[6] is in_sad[6]
--operation mode is input

in_sad[6] = INPUT();


--in_sad[7] is in_sad[7]
--operation mode is input

in_sad[7] = INPUT();


--in_sad[8] is in_sad[8]
--operation mode is input

in_sad[8] = INPUT();


--in_sad[9] is in_sad[9]
--operation mode is input

in_sad[9] = INPUT();


--in_sad[10] is in_sad[10]
--operation mode is input

in_sad[10] = INPUT();


--fig_sad_min is fig_sad_min
--operation mode is output

fig_sad_min = OUTPUT(A1L5Q);


--reg_sad[0] is reg_sad[0]
--operation mode is output

reg_sad[0] = OUTPUT(A1L67Q);


--reg_sad[1] is reg_sad[1]
--operation mode is output

reg_sad[1] = OUTPUT(A1L97Q);


--reg_sad[2] is reg_sad[2]
--operation mode is output

reg_sad[2] = OUTPUT(A1L28Q);


--reg_sad[3] is reg_sad[3]
--operation mode is output

reg_sad[3] = OUTPUT(A1L58Q);


--reg_sad[4] is reg_sad[4]
--operation mode is output

reg_sad[4] = OUTPUT(A1L88Q);


--reg_sad[5] is reg_sad[5]
--operation mode is output

reg_sad[5] = OUTPUT(A1L19Q);


--reg_sad[6] is reg_sad[6]
--operation mode is output

reg_sad[6] = OUTPUT(A1L49Q);


--reg_sad[7] is reg_sad[7]
--operation mode is output

reg_sad[7] = OUTPUT(A1L79Q);


--reg_sad[8] is reg_sad[8]
--operation mode is output

reg_sad[8] = OUTPUT(A1L001Q);


--reg_sad[9] is reg_sad[9]
--operation mode is output

reg_sad[9] = OUTPUT(A1L301Q);


--reg_sad[10] is reg_sad[10]
--operation mode is output

reg_sad[10] = OUTPUT(A1L601Q);