comp.vhd

一个比较器的实现方法

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity comp is
 port( clk:in std_logic;
       st_mv_sel:in std_logic; --使能
       comp_ready:in std_logic;--数据准备好，可以进行比较
       st_mv_table:in std_logic; --输出SAD及对应位置
       fig_sad_min:out std_logic;--输入的SAD值小，为‘1'
       in_sad:in std_logic_vector(10 downto 0);
       reg_sad:out std_logic_vector(10 downto 0)
       );
end comp;
architecture rt1 of comp is

signal reg_r1:std_logic_vector(10 downto 0); 
--signal reg_in:std_logic_vector(10 downto 0); 
begin 
   
   process(clk,st_mv_sel,reg_r1)
     begin
         if (clk'event and clk='1') then         
            if st_mv_sel='1' then
               if comp_ready='1' then
                   if in_sad >= reg_r1 then
                       fig_sad_min<='0';
                    else
                        reg_r1<=in_sad; 
                        fig_sad_min<='1';
                     end if;
                 else
                        reg_r1<=in_sad; 
                        fig_sad_min<='0';
                 end if;
               end if; 
           if st_mv_table='1' then
               reg_sad<=reg_r1;
            end if;
         end if;
    end process;       
 
end rt1;