ut.vhd

一个用外部ＭＣＵ通过ＦＰＧＡ来访问外部ＲＡＭ的文件

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-- Company: 
-- Engineer:
--
-- Create Date:    15:33:43 12/07/05
-- Design Name:    
-- Module Name:    ut - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity ut is
	port
	(
--		isa_clk : in std_logic;
		isa_addr : in std_logic_vector(12 downto 0);
		isa_cs0 : in std_logic;
		isa_cs1 : in std_logic;
		isa_wr : in std_logic;
		isa_rd : in std_logic;
--		isa_irq7 : out std_logic;
--		isa_irq9 : out std_logic;
--		isa_rstout : out std_logic;
		isa_data : inout std_logic_vector(7 downto 0);
		isa_rstin : in std_logic;

		sram_oe : out std_logic;
		sram_ce : out std_logic;
		sram_we : out std_logic;
		sram_addr : out std_logic_vector(14 downto 0);
		sram_data : inout std_logic_vector(7 downto 0);

		clk_500hz : out std_logic;

		g_clk : in std_logic
	);
end ut;

architecture Behavioral of ut is
	signal clk : std_logic;
	signal cs_ram : std_logic;
	signal reset : std_logic;
	signal addr_reg : std_logic_vector(14 downto 0);
	signal addr_hi : std_logic_vector(1 downto 0);
	signal sram_oe_s : std_logic;
	signal sram_we_s : std_logic;
	signal sram_ce_s : std_logic;
	signal isa_addr_s : std_logic_vector(12 downto 0);
	signal cnt_500hz: std_logic_vector(17 downto 0);
	signal clk_500hz_s : std_logic;
	signal data_buf : std_logic_vector(7 downto 0);
	signal addr_cnt : std_logic_vector(14 downto 0);
--	signal plus_en : std_logic;
--	signal sram_full : std_logic;
	
component Clk_DLL
	port
	(
		CLKIN : in std_logic;
		CLKOUT : out std_logic
	);
end component;

begin

ut_clk : Clk_DLL
	port map
	(
		CLKIN => g_clk,
		CLKOUT => clk
	);

clk_500hz <= clk_500hz_s;
--sram_oe <= isa_rd;
sram_oe <= sram_oe_s;
sram_we <= sram_we_s;
--sram_we <= isa_wr;
--sram_ce <= isa_cs0;
sram_ce <= sram_ce_s;

sram_oe_s <= isa_rd;
sram_we_s <= isa_wr;
sram_ce_s <= not ((not isa_cs0) and cs_ram);	

reset <= isa_rstin;
isa_addr_s <= isa_addr;
sram_addr <= addr_reg;
--sram_addr <= "00" & isa_addr;
--sram_data <= isa_data;
--isa_data <=sram_data;

get_clk_500hz : process(clk)
begin
	if (clk'event and clk = '1') then
		if (cnt_500hz = "111111111111111111") then
			clk_500hz_s <= not clk_500hz_s;
			cnt_500hz <= "111001111001010111";
		else
			cnt_500hz <= cnt_500hz + 1;
		end if;
	end if;
end process;

----reset init
reset_proc : process(reset, addr_hi, isa_addr_s)
begin
	if (reset = '0') then
		addr_reg <= "000000000000000";
	else
		addr_reg <= addr_hi & isa_addr_s;
	end if;
end process;

--write addr_hi
--0x201
reg_addr_wr : process(reset, isa_cs1, isa_wr, isa_rd, isa_addr, isa_data)
begin
	if (reset = '0') then
		addr_hi <= "00";
	elsif (isa_cs1 = '0' and isa_addr = "0001000000001" and isa_wr = '0' and isa_rd = '1') then
		addr_hi <= isa_data(1 downto 0);
	end if;
end process;

--control isa_cs0 to display's ram or to this sram
--0x203
isa_cs0_wr : process(isa_cs1, isa_wr, isa_rd, isa_addr, isa_data)
begin
	if (isa_cs1 = '0' and isa_addr = "0001000000011" and isa_wr = '0' and isa_rd = '1') then
		cs_ram <= isa_data(0);
	else
		cs_ram <= 'Z';
	end if;
end process;

--
--
sram_wr : process( sram_we_s, sram_oe_s)
begin
--	if sram_ce_s = '0' then
		if ( sram_we_s = '0' and sram_ce_s = '0' and sram_oe_s = '1') then
--			data_buf <= isa_data;
			sram_data <= isa_data;
--		end if;
		elsif (sram_oe_s = '0'and sram_ce_s = '0' and sram_we_s = '1' ) then
--			data_buf <= sram_data;
			isa_data <= sram_data;

--		end if;
	 else
--			data_buf <= "ZZZZZZZZ";
			sram_data <= "ZZZZZZZZ";
			isa_data <= "ZZZZZZZZ";

	end if;
end process;


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--control step_l 
--0x209
step_l : process(isa_cs1, isa_wr, isa_rd, isa_addr, isa_data)
begin
	if (isa_cs1 = '0' and isa_addr = "0001000001001" and isa_wr = '0' and isa_rd = '1') then
		step_l <= isa_data;
	else
		step_l <= 2;
	end if;
end process;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY max IS
	GENERIC ( m : INTEGER );
		PORT ( a : IN STD_LOGIC_VECTOR ( m-1 DOWNTO 0 );
				 c : OUT STD_LOGIC_VECTOR )





library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity comp is
 port( clk:in std_logic;
       st_mv_sel:in std_logic; --使能
       comp_ready:in std_logic;--数据准备好，可以进行比较
       st_mv_table:in std_logic; --输出SAD及对应位置
       fig_sad_min:out std_logic;--输入的SAD值小，为‘1'
       in_sad:in std_logic_vector(10 downto 0);
       reg_sad:out std_logic_vector(10 downto 0)
       );
end comp;
architecture rt1 of comp is

signal reg_r1:std_logic_vector(10 downto 0); 
--signal reg_in:std_logic_vector(10 downto 0); 
begin 
   
   process(clk,st_mv_sel,reg_r1)
     begin
         if (clk'event and clk='1') then         
            if st_mv_sel='1' then
               if comp_ready='1' then
                   if in_sad >= reg_r1 then
                       fig_sad_min<='0';
                   else
                        reg_r1<=in_sad; 
                        fig_sad_min<='1';
                   end if;
               else
                        reg_r1<=in_sad; 
                        fig_sad_min<='0';
               end if;
            end if; 
           	if st_mv_table='1' then
               reg_sad<=reg_r1;
            end if;
        end if;
    end process;       
 
end rt1;


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end Behavioral;