_info

来自「强烈推荐下载,verilog状态机实例.可以在modelsim下运行.」· 代码 · 共 41 行

m255
13
cModel Technology
dG:\taoyuhui\modelsim_work\8.10
vdflop
Ij=ii2EKGPnRWgH6SUPBPQ0
VbU7QR5:KP;_H6`2co;Zgi2
w1141046996
FG:/taoyuhui/modelsim_work/8.10/dflop.v
L0 1
VbU7QR5:KP;_H6`2co;Zgi2
OE;L;6.1b;31
r1
31
o-work work
tGenerateLoopIterationMax 100000
vshifter
ITnRFVZ:J0>JiL@R:o^oVG2
VK:c?SD=cA2lg?cIj^T2_90
w1141046996
FG:/taoyuhui/modelsim_work/8.10/dflop.v
L0 15
VK:c?SD=cA2lg?cIj^T2_90
OE;L;6.1b;31
r1
31
o-work work
tGenerateLoopIterationMax 100000
vtest
IH?j`lf@CAge^ogVMgaUzi3
Vk<3<[f=78GX=_HO53D;7>3
w1141061920
FG:/taoyuhui/modelsim_work/8.10/test.v
L0 2
Vk<3<[f=78GX=_HO53D;7>3
OE;L;6.1b;31
r1
31
o-work work
tGenerateLoopIterationMax 100000