statemachine.cr.mti

推荐下载,verilog处理器设计实例.体现了结构描述和寄存器传输描述的应用

G:/taoyuhui/modelsim_work/examples_from_books/11.2/statemachine.v {1 {vlog -work work G:/taoyuhui/modelsim_work/examples_from_books/11.2/statemachine.v
Model Technology ModelSim SE vlog 6.1b Compiler 2005.09 Sep  8 2005
-- Compiling module drink_machine

Top level modules:
	drink_machine

} {} {}}