_primary.vhd

来自「推荐下载,verilog处理器设计实例.体现了结构描述和寄存器传输描述的应用」· VHDL 代码 · 共 24 行

library verilog;
use verilog.vl_types.all;
entity drink_machine is
    generic(
        idle            : integer := 0;
        five            : integer := 1;
        ten             : integer := 2;
        twenty_five     : integer := 3;
        fifteen         : integer := 4;
        thirty          : integer := 5;
        twenty          : integer := 6
    );
    port(
        nickel_in       : in     vl_logic;
        dime_in         : in     vl_logic;
        quarter_in      : in     vl_logic;
        reset           : in     vl_logic;
        clk             : in     vl_logic;
        nickel_out      : out    vl_logic;
        dime_out        : out    vl_logic;
        dispense        : out    vl_logic
    );
end drink_machine;