st_mult1.prj

veilog实现的状态机乘法器.可以参考

#-- Synplicity, Inc.
#-- Version Synplify Pro 8.1
#-- Project file G:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.prj
#-- Written on Sat Mar 18 01:59:24 2006


#add_file options
add_file -verilog "st_mult1.v"


#implementation: "rev_3"
impl -add rev_3

#device options
set_option -technology FLEX10K
set_option -part EPF10K10
set_option -package TC144
set_option -speed_grade -3

#compilation/mapping options
set_option -default_enum_encoding default
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 0
set_option -use_fsm_explorer 0

#map options
set_option -frequency 1.000
set_option -run_prop_extract 0
set_option -fanout_limit 500
set_option -domap 1
set_option -cliquing 1
set_option -pipe 0
set_option -retiming 0
set_option -fixgatedclocks 0
set_option -no_sequential_opt 0

#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

#VIF options
set_option -write_vif 1

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "rev_3/st_mult1.edf"

#
#implementation attributes

set_option -vlog_std v2001
set_option -project_relative_includes 1

#par_1 attributes
set_option -job par_1 -add par
set_option -job par_1 -option run_backannotation 0
impl -active "rev_3"