st_mult1.prd

来自「veilog实现的状态机乘法器.可以参考」· PRD 代码 · 共 14 行

#-- Synplicity, Inc.
#-- Version Synplify Pro 8.1
#-- Project file G:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.prd
#-- Written on Sat Mar 18 01:59:24 2006

#
### Watch Implementation type ###
#
watch_impl -all
#
### Watch Implementation properties ###
#
watch_prop -clear {  Worst Slack } {  st_mult1|clk - Estimated Frequency }