st_mult1.acf

veilog实现的状态机乘法器.可以参考

--
--  Copyright (C) 1988-2001 Altera Corporation
--  Any megafunction design, and related net list (encrypted or decrypted),
--  support information, device programming or simulation file, and any other
--  associated documentation or information provided by Altera or a partner
--  under Altera's Megafunction Partnership Program may be used only to
--  program PLD devices (but not masked PLD devices) from Altera.  Any other
--  use of such megafunction design, net list, support information, device
--  programming or simulation file, or any other related documentation or
--  information is prohibited for any other purpose, including, but not
--  limited to modification, reverse engineering, de-compiling, or use with
--  any other silicon devices, unless such use is explicitly licensed under
--  a separate agreement with Altera or a megafunction partner.  Title to
--  the intellectual property, including patents, copyrights, trademarks,
--  trade secrets, or maskworks, embodied in any such megafunction design,
--  net list, support information, device programming or simulation file, or
--  any other related documentation or information provided by Altera or a
--  megafunction partner, remains with Altera, the megafunction partner, or
--  their respective licensors.  No other licenses, including any licenses
--  needed under any third party's intellectual property, are provided herein.
--
CHIP st_mult1
BEGIN
	DEVICE = EPF10K10TC144-3;
END;

DEFAULT_DEVICES
BEGIN
	AUTO_DEVICE = EPF10K70RC240-2;
	AUTO_DEVICE = EPF10K50BC356-3;
	AUTO_DEVICE = EPF10K50RC240-3;
	AUTO_DEVICE = EPF10K40RC240-3;
	AUTO_DEVICE = EPF10K40RC208-3;
	AUTO_DEVICE = EPF10K30BC356-3;
	AUTO_DEVICE = EPF10K30RC240-3;
	AUTO_DEVICE = EPF10K30RC208-3;
	AUTO_DEVICE = EPF10K20RC240-3;
	AUTO_DEVICE = EPF10K20RC208-3;
	AUTO_DEVICE = EPF10K20TC144-3;
	AUTO_DEVICE = EPF10K10QC208-3;
	AUTO_DEVICE = EPF10K10TC144-3;
	AUTO_DEVICE = EPF10K10LC84-3;
	ASK_BEFORE_ADDING_EXTRA_DEVICES = ON;
END;

TIMING_POINT
BEGIN
	MAINTAIN_STABLE_SYNTHESIS = ON;
	DEVICE_FOR_TIMING_SYNTHESIS = EPF10K10LC84-3;
	CUT_ALL_CLEAR_PRESET = ON;
	CUT_ALL_BIDIR = ON;
	FREQUENCY = 1.0MHz;
	|Clock :	FREQUENCY = 1.0MHz;
	|Done :	TCO = 999.9ns;
	|Acc0 :	TCO = 999.9ns;
	|Acc1 :	TCO = 999.9ns;
	|Acc2 :	TCO = 999.9ns;
	|Acc3 :	TCO = 999.9ns;
	|Acc4 :	TCO = 999.9ns;
	|Acc5 :	TCO = 999.9ns;
	|Acc6 :	TCO = 999.9ns;
	|Acc7 :	TCO = 999.9ns;
	|Acc8 :	TCO = 999.9ns;
	|Acc9 :	TCO = 999.9ns;
	|Acc10 :	TCO = 999.9ns;
	|Acc11 :	TCO = 999.9ns;
	|Acc12 :	TCO = 999.9ns;
	|Acc13 :	TCO = 999.9ns;
	|Acc14 :	TCO = 999.9ns;
	|Acc15 :	TCO = 999.9ns;
	|Acc16 :	TCO = 999.9ns;
	|Acc17 :	TCO = 999.9ns;
	|Acc18 :	TCO = 999.9ns;
	|Acc19 :	TCO = 999.9ns;
	|Acc20 :	TCO = 999.9ns;
	|Acc21 :	TCO = 999.9ns;
	|Acc22 :	TCO = 999.9ns;
	|Acc23 :	TCO = 999.9ns;
	|Acc24 :	TCO = 999.9ns;
	|Acc25 :	TCO = 999.9ns;
	|Acc26 :	TCO = 999.9ns;
	|Acc27 :	TCO = 999.9ns;
	|Acc28 :	TCO = 999.9ns;
	|Acc29 :	TCO = 999.9ns;
	|Acc30 :	TCO = 999.9ns;
	|Acc31 :	TCO = 999.9ns;
	|Mplr0 :	TSU = 999.9ns;
	|Mplr1 :	TSU = 999.9ns;
	|Mplr2 :	TSU = 999.9ns;
	|Mplr3 :	TSU = 999.9ns;
	|Mplr4 :	TSU = 999.9ns;
	|Mplr5 :	TSU = 999.9ns;
	|Mplr6 :	TSU = 999.9ns;
	|Mplr7 :	TSU = 999.9ns;
	|Mplr8 :	TSU = 999.9ns;
	|Mplr9 :	TSU = 999.9ns;
	|Mplr10 :	TSU = 999.9ns;
	|Mplr11 :	TSU = 999.9ns;
	|Mplr12 :	TSU = 999.9ns;
	|Mplr13 :	TSU = 999.9ns;
	|Mplr14 :	TSU = 999.9ns;
	|Mplr15 :	TSU = 999.9ns;
	|Mcnd0 :	TSU = 999.9ns;
	|Mcnd1 :	TSU = 999.9ns;
	|Mcnd2 :	TSU = 999.9ns;
	|Mcnd3 :	TSU = 999.9ns;
	|Mcnd4 :	TSU = 999.9ns;
	|Mcnd5 :	TSU = 999.9ns;
	|Mcnd6 :	TSU = 999.9ns;
	|Mcnd7 :	TSU = 999.9ns;
	|Mcnd8 :	TSU = 999.9ns;
	|Mcnd9 :	TSU = 999.9ns;
	|Mcnd10 :	TSU = 999.9ns;
	|Mcnd11 :	TSU = 999.9ns;
	|Mcnd12 :	TSU = 999.9ns;
	|Mcnd13 :	TSU = 999.9ns;
	|Mcnd14 :	TSU = 999.9ns;
	|Mcnd15 :	TSU = 999.9ns;
	|Clock :	TSU = 999.9ns;
	|Reset :	TSU = 999.9ns;
	|clk :	FREQUENCY = 1.0MHz;
	|ok :	TCO = 999.9ns;
	|result0 :	TCO = 999.9ns;
	|result1 :	TCO = 999.9ns;
	|result2 :	TCO = 999.9ns;
	|result3 :	TCO = 999.9ns;
	|result4 :	TCO = 999.9ns;
	|result5 :	TCO = 999.9ns;
	|result6 :	TCO = 999.9ns;
	|result7 :	TCO = 999.9ns;
	|result8 :	TCO = 999.9ns;
	|result9 :	TCO = 999.9ns;
	|result10 :	TCO = 999.9ns;
	|result11 :	TCO = 999.9ns;
	|result12 :	TCO = 999.9ns;
	|result13 :	TCO = 999.9ns;
	|result14 :	TCO = 999.9ns;
	|result15 :	TCO = 999.9ns;
	|result16 :	TCO = 999.9ns;
	|result17 :	TCO = 999.9ns;
	|result18 :	TCO = 999.9ns;
	|result19 :	TCO = 999.9ns;
	|result20 :	TCO = 999.9ns;
	|result21 :	TCO = 999.9ns;
	|result22 :	TCO = 999.9ns;
	|result23 :	TCO = 999.9ns;
	|result24 :	TCO = 999.9ns;
	|result25 :	TCO = 999.9ns;
	|result26 :	TCO = 999.9ns;
	|result27 :	TCO = 999.9ns;
	|result28 :	TCO = 999.9ns;
	|result29 :	TCO = 999.9ns;
	|result30 :	TCO = 999.9ns;
	|result31 :	TCO = 999.9ns;
	|cheng_shu0 :	TSU = 999.9ns;
	|cheng_shu1 :	TSU = 999.9ns;
	|cheng_shu2 :	TSU = 999.9ns;
	|cheng_shu3 :	TSU = 999.9ns;
	|cheng_shu4 :	TSU = 999.9ns;
	|cheng_shu5 :	TSU = 999.9ns;
	|cheng_shu6 :	TSU = 999.9ns;
	|cheng_shu7 :	TSU = 999.9ns;
	|cheng_shu8 :	TSU = 999.9ns;
	|cheng_shu9 :	TSU = 999.9ns;
	|cheng_shu10 :	TSU = 999.9ns;
	|cheng_shu11 :	TSU = 999.9ns;
	|cheng_shu12 :	TSU = 999.9ns;
	|cheng_shu13 :	TSU = 999.9ns;
	|cheng_shu14 :	TSU = 999.9ns;
	|cheng_shu15 :	TSU = 999.9ns;
	|bei_cheng_shu0 :	TSU = 999.9ns;
	|bei_cheng_shu1 :	TSU = 999.9ns;
	|bei_cheng_shu2 :	TSU = 999.9ns;
	|bei_cheng_shu3 :	TSU = 999.9ns;
	|bei_cheng_shu4 :	TSU = 999.9ns;
	|bei_cheng_shu5 :	TSU = 999.9ns;
	|bei_cheng_shu6 :	TSU = 999.9ns;
	|bei_cheng_shu7 :	TSU = 999.9ns;
	|bei_cheng_shu8 :	TSU = 999.9ns;
	|bei_cheng_shu9 :	TSU = 999.9ns;
	|bei_cheng_shu10 :	TSU = 999.9ns;
	|bei_cheng_shu11 :	TSU = 999.9ns;
	|bei_cheng_shu12 :	TSU = 999.9ns;
	|bei_cheng_shu13 :	TSU = 999.9ns;
	|bei_cheng_shu14 :	TSU = 999.9ns;
	|bei_cheng_shu15 :	TSU = 999.9ns;
	|clk :	TSU = 999.9ns;
	|rst :	TSU = 999.9ns;
END;

IGNORED_ASSIGNMENTS
BEGIN
	DEMOTE_SPECIFIC_LCELL_ASSIGNMENTS_TO_LAB_ASSIGNMENTS = OFF;
	IGNORE_LOCAL_ROUTING_ASSIGNMENTS = OFF;
	IGNORE_DEVICE_ASSIGNMENTS = OFF;
	IGNORE_LC_ASSIGNMENTS = OFF;
	IGNORE_PIN_ASSIGNMENTS = OFF;
	IGNORE_CHIP_ASSIGNMENTS = OFF;
	IGNORE_TIMING_ASSIGNMENTS = OFF;
	IGNORE_LOGIC_OPTION_ASSIGNMENTS = OFF;
	IGNORE_CLIQUE_ASSIGNMENTS = OFF;
	FIT_IGNORE_TIMING = OFF;
END;

GLOBAL_PROJECT_DEVICE_OPTIONS
BEGIN
	MAX7000B_ENABLE_VREFB = OFF;
	MAX7000B_ENABLE_VREFA = OFF;
	MAX7000B_VCCIO_IOBANK2 = 3.3V;
	MAX7000B_VCCIO_IOBANK1 = 3.3V;
	CONFIG_EPROM_PULLUP_RESISTOR = ON;
	CONFIG_EPROM_USER_CODE = FFFFFFFF;
	FLEX_CONFIGURATION_EPROM = AUTO;
	MAX7000AE_ENABLE_JTAG = ON;
	MAX7000AE_USER_CODE = FFFFFFFF;
	FLEX6000_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
	FLEX10KA_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = ON;
	FLEX10K_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
	FLEX6000_ENABLE_JTAG = OFF;
	CONFIG_SCHEME_FLEX_6000 = PASSIVE_SERIAL;
	MULTIVOLT_IO = OFF;
	MAX7000S_ENABLE_JTAG = ON;
	FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
	MAX7000S_USER_CODE = FFFF;
	CONFIG_SCHEME_10K = PASSIVE_SERIAL;
	FLEX10K_JTAG_USER_CODE = 7F;
	ENABLE_INIT_DONE_OUTPUT = OFF;
	ENABLE_CHIP_WIDE_OE = OFF;
	ENABLE_CHIP_WIDE_RESET = OFF;
	nCEO = UNRESERVED;
	CLKUSR = UNRESERVED;
	ADD17 = UNRESERVED;
	ADD16 = UNRESERVED;
	ADD15 = UNRESERVED;
	ADD14 = UNRESERVED;
	ADD13 = UNRESERVED;
	ADD0_TO_ADD12 = UNRESERVED;
	SDOUT = RESERVED_DRIVES_OUT;
	RDCLK = UNRESERVED;
	RDYnBUSY = UNRESERVED;
	nWS_nRS_nCS_CS = UNRESERVED;
	DATA1_TO_DATA7 = UNRESERVED;
	DATA0 = RESERVED_TRI_STATED;
	FLEX8000_ENABLE_JTAG = OFF;
	CONFIG_SCHEME = ACTIVE_SERIAL;
	DISABLE_TIME_OUT = OFF;
	ENABLE_DCLK_OUTPUT = OFF;
	RELEASE_CLEARS = OFF;
	AUTO_RESTART = OFF;
	USER_CLOCK = OFF;
	SECURITY_BIT = OFF;
	RESERVED_PINS_PERCENT = 0;
	RESERVED_LCELLS_PERCENT = 0;
END;

GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS
BEGIN
	MULTI_LEVEL_SYNTHESIS_MAX9000 = ON;
	AUTO_IMPLEMENT_IN_EAB = OFF;
	AUTO_OPEN_DRAIN_PINS = ON;
	ONE_HOT_STATE_MACHINE_ENCODING = OFF;
	AUTO_REGISTER_PACKING = OFF;
	AUTO_FAST_IO = OFF;
	AUTO_GLOBAL_OE = ON;
	AUTO_GLOBAL_PRESET = ON;
	AUTO_GLOBAL_CLEAR = ON;
	AUTO_GLOBAL_CLOCK = ON;
	MULTI_LEVEL_SYNTHESIS_MAX5000_7000 = OFF;
	OPTIMIZE_FOR_SPEED = 5;
	DEVICE_FAMILY = FLEX10K;
	STYLE = WYSIWYG;
END;

COMPILER_PROCESSING_CONFIGURATION
BEGIN
	PRESERVE_ALL_NODE_NAME_SYNONYMS = OFF;
	FITTER_SETTINGS = NORMAL;
	SMART_RECOMPILE = OFF;
	GENERATE_AHDL_TDO_FILE = OFF;
	RPT_FILE_USER_ASSIGNMENTS = ON;
	RPT_FILE_LCELL_INTERCONNECT = ON;
	RPT_FILE_HIERARCHY = ON;
	RPT_FILE_EQUATIONS = ON;
	LINKED_SNF_EXTRACTOR = OFF;
	OPTIMIZE_TIMING_SNF = OFF;
	TIMING_SNF_EXTRACTOR = ON;
	FUNCTIONAL_SNF_EXTRACTOR = OFF;
	DESIGN_DOCTOR_RULES = EPLD;
	DESIGN_DOCTOR = OFF;
END;

COMPILER_INTERFACES_CONFIGURATION
BEGIN
	NETLIST_OUTPUT_TIME_SCALE = 0.1ns;
	EDIF_INPUT_SHOW_LMF_MAPPING_MESSAGES = OFF;
	EDIF_BUS_DELIMITERS = [];
	EDIF_FLATTEN_BUS = OFF;
	EDIF_OUTPUT_FORCE_0NS_DELAYS = OFF;
	EDIF_OUTPUT_INCLUDE_SPECIAL_PRIM = OFF;
	EDIF_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
	EDIF_OUTPUT_DELAY_CONSTRUCTS = EDO_FILE;
	EDIF_OUTPUT_USE_EDC = OFF;
	EDIF_INPUT_USE_LMF2 = OFF;
	EDIF_OUTPUT_GND = GND;
	EDIF_OUTPUT_VCC = VCC;
	EDIF_OUTPUT_EDC_FILE = *.edc;
	EDIF_INPUT_LMF2 = *.lmf;
	VHDL_GENERATE_CONFIGURATION_DECLARATION = OFF;
	VHDL_OUTPUT_DELAY_CONSTRUCTS = VHO_FILE;
	VERILOG_OUTPUT_DELAY_CONSTRUCTS = VO_FILE;
	VHDL_FLATTEN_BUS = OFF;
	VERILOG_FLATTEN_BUS = OFF;
	EDIF_TRUNCATE_HIERARCHY_PATH = OFF;
	VHDL_TRUNCATE_HIERARCHY_PATH = OFF;
	VERILOG_TRUNCATE_HIERARCHY_PATH = OFF;
	VERILOG_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
	VHDL_WRITER_VERSION = VHDL93;
	VHDL_READER_VERSION = VHDL93;
	SYNOPSYS_MAPPING_EFFORT = MEDIUM;
	SYNOPSYS_BOUNDARY_OPTIMIZATION = OFF;
	SYNOPSYS_HIERARCHICAL_COMPILATION = ON;
	SYNOPSYS_DESIGNWARE = OFF;
	SYNOPSYS_COMPILER = DESIGN;
	USE_SYNOPSYS_SYNTHESIS = OFF;
	VHDL_NETLIST_WRITER = OFF;
	VERILOG_NETLIST_WRITER = OFF;
	XNF_GENERATE_AHDL_TDX_FILE = ON;
	XNF_TRANSLATE_INTERNAL_NODE_NAMES = ON;
	XNF_EMULATE_TRI_STATE_BUSES = INTERNAL_LOGIC;
	EDIF_OUTPUT_VERSION = 200;
	EDIF_NETLIST_WRITER = OFF;
	EDIF_INPUT_GND = GND;
	EDIF_INPUT_VCC = VCC;
	EDIF_INPUT_LMF1 = synplcty.lmf;
	EDIF_INPUT_USE_LMF1 = ON;
END;

CUSTOM_DESIGN_DOCTOR_RULES
BEGIN
	MASTER_RESET = OFF;
	EXPANDER_NETWORKS = ON;
	RACE_CONDITIONS = ON;
	DELAY_CHAINS = ON;
	ASYNCHRONOUS_INPUTS = ON;
	PRESET_CLEAR_NETWORKS = ON;
	STATIC_HAZARDS_AFTER_SYNTHESIS = OFF;
	STATIC_HAZARDS_BEFORE_SYNTHESIS = ON;
	MULTI_CLOCK_NETWORKS = ON;
	MULTI_LEVEL_CLOCKS = ON;
	GATED_CLOCKS = ON;
	RIPPLE_CLOCKS = ON;
END;

SIMULATOR_CONFIGURATION
BEGIN
	END_TIME = 10.0us;