📄 st_mult1.rpt
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- 7 - B 17 OR2 0 3 0 2 |lpm_latch:bei_cheng_shu_Temp_21_|:49
- 1 - B 17 OR2 0 3 0 2 |lpm_latch:bei_cheng_shu_Temp_22_|:49
- 7 - B 13 OR2 0 3 0 2 |lpm_latch:bei_cheng_shu_Temp_23_|:49
- 3 - C 16 OR2 0 3 0 2 |lpm_latch:bei_cheng_shu_Temp_24_|:49
- 4 - C 16 OR2 0 3 0 2 |lpm_latch:bei_cheng_shu_Temp_25_|:49
- 7 - C 16 OR2 0 3 0 2 |lpm_latch:bei_cheng_shu_Temp_26_|:49
- 2 - C 16 OR2 0 3 0 2 |lpm_latch:bei_cheng_shu_Temp_27_|:49
- 1 - C 18 OR2 0 3 0 2 |lpm_latch:bei_cheng_shu_Temp_28_|:49
- 2 - C 18 OR2 0 3 0 2 |lpm_latch:bei_cheng_shu_Temp_29_|:49
- 3 - C 18 OR2 0 3 0 2 |lpm_latch:bei_cheng_shu_Temp_30_|:49
- 5 - C 18 OR2 0 3 0 1 |lpm_latch:bei_cheng_shu_Temp_31_|:49
- 3 - A 08 OR2 0 2 0 6 |lpm_latch:count_0_|:49
- 5 - A 09 OR2 0 3 0 4 |lpm_latch:count_1_|:49
- 8 - A 18 OR2 0 3 0 10 |lpm_latch:count_2_|:49
- 4 - A 06 OR2 0 3 0 10 |lpm_latch:count_3_|:49
- 2 - A 04 OR2 0 3 0 2 |lpm_latch:count_4_|:49
- 2 - A 11 OR2 0 3 0 2 |lpm_latch:count_5_|:49
- 5 - A 06 OR2 0 3 0 2 |lpm_latch:count_6_|:49
- 4 - A 08 OR2 0 3 0 2 |lpm_latch:count_7_|:49
- 8 - A 06 OR2 0 3 0 2 |lpm_latch:count_8_|:49
- 2 - A 06 OR2 0 3 0 2 |lpm_latch:count_9_|:49
- 7 - A 06 OR2 0 3 0 2 |lpm_latch:count_10_|:49
- 8 - A 09 OR2 0 3 0 2 |lpm_latch:count_11_|:49
- 6 - A 06 OR2 0 3 0 2 |lpm_latch:count_12_|:49
- 7 - A 09 OR2 0 3 0 2 |lpm_latch:count_13_|:49
- 6 - A 09 OR2 0 3 0 2 |lpm_latch:count_14_|:49
- 2 - A 03 OR2 0 3 0 2 |lpm_latch:count_15_|:49
- 5 - A 03 OR2 0 3 0 2 |lpm_latch:count_16_|:49
- 8 - A 03 OR2 0 3 0 2 |lpm_latch:count_17_|:49
- 1 - A 03 OR2 0 3 0 2 |lpm_latch:count_18_|:49
- 4 - A 13 OR2 0 3 0 2 |lpm_latch:count_19_|:49
- 6 - A 02 OR2 0 3 0 2 |lpm_latch:count_20_|:49
- 5 - A 02 OR2 0 3 0 2 |lpm_latch:count_21_|:49
- 7 - A 02 OR2 0 3 0 2 |lpm_latch:count_22_|:49
- 4 - A 02 OR2 0 3 0 2 |lpm_latch:count_23_|:49
- 2 - A 08 OR2 0 3 0 2 |lpm_latch:count_24_|:49
- 8 - A 02 OR2 0 3 0 2 |lpm_latch:count_25_|:49
- 3 - A 06 OR2 0 3 0 2 |lpm_latch:count_26_|:49
- 7 - A 08 OR2 0 3 0 2 |lpm_latch:count_27_|:49
- 6 - A 08 OR2 0 3 0 2 |lpm_latch:count_28_|:49
- 5 - A 08 OR2 0 3 0 2 |lpm_latch:count_29_|:49
- 8 - A 08 OR2 0 3 0 2 |lpm_latch:count_30_|:49
- 1 - A 06 OR2 0 3 0 1 |lpm_latch:count_31_|:49
- 5 - B 15 OR2 0 4 0 1 |lpm_latch:state_temp_0_|clrn0
- 7 - B 15 AND2 ! 0 2 0 1 |lpm_latch:state_temp_0_|prn0
- 8 - B 15 OR2 0 2 0 2 |lpm_latch:state_temp_0_|:49
- 1 - C 19 OR2 1 3 0 1 |lpm_latch:state_temp_1_|clrn0
- 4 - C 19 OR2 ! 0 4 0 1 |lpm_latch:state_temp_1_|prn0
- 5 - C 19 OR2 0 2 0 3 |lpm_latch:state_temp_1_|:49
- 1 - A 05 LCELL 0 2 0 3 N_36_lx_0 (N_36_clc)
- 2 - A 05 LCELL 0 2 0 3 N_37_lx_0 (N_37_clc)
- 2 - A 10 LCELL 0 2 0 3 N_38_lx_0 (N_38_clc)
- 3 - A 10 LCELL 0 2 0 3 N_40_lx_0 (N_40_clc)
- 4 - A 05 LCELL 0 2 0 3 N_41_lx_0 (N_41_clc)
- 4 - A 10 LCELL 0 2 0 3 N_42_lx_0 (N_42_clc)
- 5 - A 05 LCELL 0 2 0 3 N_43_lx_0 (N_43_clc)
- 5 - A 10 LCELL 0 2 0 3 N_44_lx_0 (N_44_clc)
- 6 - A 05 LCELL 0 2 0 3 N_45_lx_0 (N_45_clc)
- 6 - A 10 LCELL 0 2 0 3 N_46_lx_0 (N_46_clc)
- 7 - A 05 LCELL 0 2 0 3 N_47_lx_0 (N_47_clc)
- 7 - A 10 LCELL 0 2 0 3 N_48_lx_0 (N_48_clc)
- 8 - A 05 LCELL 0 2 0 3 N_49_lx_0 (N_49_clc)
- 8 - A 10 LCELL 0 2 0 2 N_50_lx_0 (N_50_clc)
- 1 - A 07 LCELL 0 2 0 2 N_51_lx_0 (N_51_clc)
- 1 - A 12 LCELL 0 2 0 2 N_52_lx_0 (N_52_clc)
- 2 - A 07 LCELL 0 2 0 2 N_53_lx_0 (N_53_clc)
- 2 - A 12 LCELL 0 2 0 2 N_54_lx_0 (N_54_clc)
- 3 - A 07 LCELL 0 2 0 2 N_55_lx_0 (N_55_clc)
- 3 - A 12 LCELL 0 2 0 2 N_56_lx_0 (N_56_clc)
- 4 - A 07 LCELL 0 2 0 2 N_57_lx_0 (N_57_clc)
- 4 - A 12 LCELL 0 2 0 2 N_58_lx_0 (N_58_clc)
- 5 - A 07 LCELL 0 2 0 2 N_59_lx_0 (N_59_clc)
- 5 - A 12 LCELL 0 2 0 2 N_60_lx_0 (N_60_clc)
- 6 - A 07 LCELL 0 2 0 2 N_61_lx_0 (N_61_clc)
- 6 - A 12 LCELL 0 2 0 2 N_62_lx_0 (N_62_clc)
- 7 - A 07 LCELL 0 2 0 2 N_63_lx_0 (N_63_clc)
- 7 - A 12 LCELL 0 2 0 2 N_64_lx_0 (N_64_clc)
- 8 - A 07 LCELL 0 1 0 2 N_65_OUT (N_65)
- 8 - A 12 LCELL 0 2 0 3 N_66_OUT (N_66)
- 3 - B 15 OR2 1 3 0 2 N_429_i~1
- 3 - A 09 CASCADE 0 5 0 1 N_4 (ok_0_a2_cas)
- 1 - A 08 AND2 ! 0 4 0 2 ok_0_a2_2_0_i~9
- 4 - A 03 AND2 0 4 0 2 ok_0_a2_14_0_2~3
- 2 - A 01 CASCADE 0 4 0 1 N_12 (ok_0_a2_14_0_9_cas)
- 1 - A 09 CASCADE 0 4 0 1 N_30 (ok_0_a2_14_0_9_rep1_cas)
- 2 - A 09 CASCADE 0 5 0 1 N_10 (ok_0_a2_14_0_13_cas)
- 3 - A 01 CASCADE 0 5 0 1 N_28 (ok_0_a2_14_0_13_rep0_cas)
- 4 - A 09 LCELL 0 5 1 0 ok_0_a2
- 3 - C 23 AND2 0 4 1 0 result_0_~1
- 2 - C 23 AND2 0 4 1 0 result_1_~1
- 7 - C 13 AND2 0 4 1 0 result_2_~1
- 3 - C 13 AND2 0 4 1 0 result_3_~1
- 4 - B 13 AND2 0 4 1 0 result_4_~1
- 1 - A 14 AND2 0 4 1 0 result_5_~1
- 4 - A 14 AND2 0 4 1 0 result_6_~1
- 2 - B 13 AND2 0 4 1 0 result_7_~1
- 3 - B 12 AND2 0 4 1 0 result_8_~1
- 2 - B 12 AND2 0 4 1 0 result_9_~1
- 6 - B 13 AND2 0 4 1 0 result_10_~1
- 2 - B 03 AND2 0 4 1 0 result_11_~1
- 4 - B 03 AND2 0 4 1 0 result_12_~1
- 2 - B 15 AND2 0 4 1 0 result_13_~1
- 1 - B 23 AND2 0 4 1 0 result_14_~1
- 7 - B 23 AND2 0 4 1 0 result_15_~1
- 4 - B 23 AND2 0 4 1 0 result_16_~1
- 8 - B 13 AND2 0 4 1 0 result_17_~1
- 8 - B 17 AND2 0 4 1 0 result_18_~1
- 3 - B 13 AND2 0 4 1 0 result_19_~1
- 2 - B 17 AND2 0 4 1 0 result_20_~1
- 5 - B 17 AND2 0 4 1 0 result_21_~1
- 5 - B 13 AND2 0 4 1 0 result_22_~1
- 1 - B 13 AND2 0 4 1 0 result_23_~1
- 5 - C 16 AND2 0 4 1 0 result_24_~1
- 6 - C 16 AND2 0 4 1 0 result_25_~1
- 1 - C 16 AND2 0 4 1 0 result_26_~1
- 8 - C 16 AND2 0 4 1 0 result_27_~1
- 7 - C 18 AND2 0 4 1 0 result_28_~1
- 8 - C 18 AND2 0 4 1 0 result_29_~1
- 4 - C 18 AND2 0 4 1 0 result_30_~1
- 6 - C 18 AND2 0 4 1 0 result_31_~1
- 6 - B 15 OR2 ! 1 2 0 63 state_temp_0_sqmuxa_0_o2~2
- 5 - A 01 CASCADE 0 5 0 1 N_14 (state_temp_1_i_a2_0_cas_0_)
- 6 - A 01 LCELL 0 5 0 1 state_temp_1_i_a2_0_0_ (state_temp_1_i_a2_0_0)
- 4 - A 01 CASCADE 0 5 0 1 N_16 (state_temp_1_i_a2_0_2_cas_0_)
- 1 - A 02 CASCADE 0 4 0 1 N_8 (state_temp_1_i_a2_0_10_cas_0_)
- 2 - A 02 LCELL 0 5 0 2 state_temp_1_i_a2_0_10_0_ (state_temp_1_i_a2_0_10_lc_0_)
- 3 - C 19 AND2 1 3 0 1 state_temp_1_0_a2_1_~3
- 3 - A 15 CASCADE 2 2 0 1 N_26 (un1_cheng_shu_3_0_cas)
- 5 - A 15 CASCADE 2 2 0 1 N_24 (un1_cheng_shu_6_0_cas)
- 1 - A 23 CASCADE 2 2 0 1 N_22 (un1_cheng_shu_10_0_cas)
- 1 - A 15 CASCADE 2 2 0 1 N_20 (un1_cheng_shu_13_0_cas)
- 7 - A 15 CASCADE 0 4 0 1 N_18 (un1_cheng_shu_15_0_i_m2_cas)
- 6 - C 19 OR2 1 2 0 47 un1_current_state_1_i_0~6
- 4 - C 23 OR2 ! 1 1 0 1 un1_rst_1_0_o2~1
- 3 - A 05 LCELL 0 2 0 3 un9_count_lx_0_4_ (un9_count_clc_4_)
- 3 - A 02 LCELL 0 5 0 1 ok_0_a2_2 (:204)
- 8 - A 15 LCELL 0 5 0 34 un1_cheng_shu_15_0_i_m2 (:218)
- 2 - A 15 LCELL 2 3 0 1 un1_cheng_shu_13_0 (:221)
- 2 - A 23 LCELL 2 3 0 1 un1_cheng_shu_10_0 (:224)
- 6 - A 15 LCELL 2 3 0 1 un1_cheng_shu_6_0 (:227)
- 4 - A 15 LCELL 2 3 0 1 un1_cheng_shu_3_0 (:230)
- 1 - A 10 CARRY 0 2 0 1 |carry_sum:N_36_cry|:31
- 2 - A 05 CARRY 0 3 0 1 |carry_sum:N_37_cry|:31
- 2 - A 10 CARRY 0 3 0 1 |carry_sum:N_38_cry|:31
- 3 - A 10 CARRY 0 3 0 1 |carry_sum:N_40_cry|:31
- 4 - A 05 CARRY 0 3 0 1 |carry_sum:N_41_cry|:31
- 4 - A 10 CARRY 0 3 0 1 |carry_sum:N_42_cry|:31
- 5 - A 05 CARRY 0 3 0 1 |carry_sum:N_43_cry|:31
- 5 - A 10 CARRY 0 3 0 1 |carry_sum:N_44_cry|:31
- 6 - A 05 CARRY 0 3 0 1 |carry_sum:N_45_cry|:31
- 6 - A 10 CARRY 0 3 0 1 |carry_sum:N_46_cry|:31
- 7 - A 05 CARRY 0 3 0 1 |carry_sum:N_47_cry|:31
- 7 - A 10 CARRY 0 3 0 1 |carry_sum:N_48_cry|:31
- 8 - A 05 CARRY 0 3 0 1 |carry_sum:N_49_cry|:31
- 8 - A 10 CARRY 0 3 0 1 |carry_sum:N_50_cry|:31
- 1 - A 07 CARRY 0 3 0 1 |carry_sum:N_51_cry|:31
- 1 - A 12 CARRY 0 3 0 1 |carry_sum:N_52_cry|:31
- 2 - A 07 CARRY 0 3 0 1 |carry_sum:N_53_cry|:31
- 2 - A 12 CARRY 0 3 0 1 |carry_sum:N_54_cry|:31
- 3 - A 07 CARRY 0 3 0 1 |carry_sum:N_55_cry|:31
- 3 - A 12 CARRY 0 3 0 1 |carry_sum:N_56_cry|:31
- 4 - A 07 CARRY 0 3 0 1 |carry_sum:N_57_cry|:31
- 4 - A 12 CARRY 0 3 0 1 |carry_sum:N_58_cry|:31
- 5 - A 07 CARRY 0 3 0 1 |carry_sum:N_59_cry|:31
- 5 - A 12 CARRY 0 3 0 1 |carry_sum:N_60_cry|:31
- 6 - A 07 CARRY 0 3 0 1 |carry_sum:N_61_cry|:31
- 6 - A 12 CARRY 0 3 0 1 |carry_sum:N_62_cry|:31
- 7 - A 07 CARRY 0 3 0 1 |carry_sum:N_63_cry|:31
- 7 - A 12 CARRY 0 3 0 1 |carry_sum:N_64_cry|:31
- 3 - A 05 CARRY 0 3 0 1 |carry_sum:un9_count_cry_4_|:31
- 1 - A 05 CARRY 0 2 0 1 un9_count_COUT_0_ (un9_count_cry_0_)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:g:\taoyuhui\synplifywork_new\statemachine_mult\rev_2\maxplus\st_mult1.rpt
st_mult1
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
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