📄 st_mult1.rpt
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Total input pins required: 34
Total input I/O cell registers required: 0
Total output pins required: 33
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 181
Total flipflops required: 2
Total packed registers required: 0
Total logic cells in carry chains: 32
Total number of carry chains: 2
Total number of carry chains of length 1-8 : 0
Total number of carry chains of length 9-16: 2
Total logic cells in cascade chains: 22
Total number of cascade chains: 8
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 0/ 576 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 5 8 5 1 8 8 8 8 8 8 1 8 0 1 8 8 0 0 1 0 0 0 0 2 0 96/0
B: 0 0 8 0 0 0 0 0 0 0 0 8 0 8 0 8 0 8 0 0 0 0 0 8 0 48/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 7 0 0 8 0 8 7 0 0 0 7 0 37/0
Total: 5 8 13 1 8 8 8 8 8 8 1 16 0 16 8 16 8 8 9 7 0 0 0 17 0 181/0
Device-Specific Information:g:\taoyuhui\synplifywork_new\statemachine_mult\rev_2\maxplus\st_mult1.rpt
st_mult1
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
83 - - C -- INPUT 0 0 0 1 bei_cheng_shu0
82 - - C -- INPUT 0 0 0 1 bei_cheng_shu1
79 - - C -- INPUT 0 0 0 1 bei_cheng_shu2
80 - - C -- INPUT 0 0 0 1 bei_cheng_shu3
81 - - C -- INPUT 0 0 0 1 bei_cheng_shu4
14 - - A -- INPUT 0 0 0 1 bei_cheng_shu5
102 - - A -- INPUT 0 0 0 1 bei_cheng_shu6
97 - - A -- INPUT 0 0 0 1 bei_cheng_shu7
90 - - B -- INPUT 0 0 0 1 bei_cheng_shu8
87 - - B -- INPUT 0 0 0 1 bei_cheng_shu9
68 - - - 07 INPUT 0 0 0 1 bei_cheng_shu10
70 - - - 05 INPUT 0 0 0 1 bei_cheng_shu11
121 - - - 10 INPUT 0 0 0 1 bei_cheng_shu12
122 - - - 12 INPUT 0 0 0 1 bei_cheng_shu13
92 - - B -- INPUT 0 0 0 1 bei_cheng_shu14
88 - - B -- INPUT 0 0 0 1 bei_cheng_shu15
131 - - - 15 INPUT 0 0 0 1 cheng_shu0
126 - - - -- INPUT 0 0 0 1 cheng_shu1
9 - - A -- INPUT 0 0 0 1 cheng_shu2
13 - - A -- INPUT 0 0 0 1 cheng_shu3
100 - - A -- INPUT 0 0 0 1 cheng_shu4
56 - - - -- INPUT 0 0 0 1 cheng_shu5
95 - - A -- INPUT 0 0 0 1 cheng_shu6
12 - - A -- INPUT 0 0 0 1 cheng_shu7
7 - - A -- INPUT 0 0 0 1 cheng_shu8
125 - - - -- INPUT 0 0 0 1 cheng_shu9
98 - - A -- INPUT 0 0 0 1 cheng_shu10
101 - - A -- INPUT 0 0 0 1 cheng_shu11
138 - - - 20 INPUT 0 0 0 1 cheng_shu12
124 - - - -- INPUT 0 0 0 1 cheng_shu13
96 - - A -- INPUT 0 0 0 1 cheng_shu14
11 - - A -- INPUT 0 0 0 1 cheng_shu15
55 - - - -- INPUT G 0 0 0 0 CLK
54 - - - -- INPUT 0 0 0 8 rst
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information:g:\taoyuhui\synplifywork_new\statemachine_mult\rev_2\maxplus\st_mult1.rpt
st_mult1
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
99 - - A -- OUTPUT 0 1 0 0 ok
142 - - - 23 OUTPUT 0 1 0 0 result0
27 - - C -- OUTPUT 0 1 0 0 result1
78 - - C -- OUTPUT 0 1 0 0 result2
28 - - C -- OUTPUT 0 1 0 0 result3
130 - - - 14 OUTPUT 0 1 0 0 result4
8 - - A -- OUTPUT 0 1 0 0 result5
10 - - A -- OUTPUT 0 1 0 0 result6
91 - - B -- OUTPUT 0 1 0 0 result7
60 - - - 12 OUTPUT 0 1 0 0 result8
62 - - - 11 OUTPUT 0 1 0 0 result9
22 - - B -- OUTPUT 0 1 0 0 result10
112 - - - 03 OUTPUT 0 1 0 0 result11
114 - - - 04 OUTPUT 0 1 0 0 result12
18 - - B -- OUTPUT 0 1 0 0 result13
17 - - B -- OUTPUT 0 1 0 0 result14
23 - - B -- OUTPUT 0 1 0 0 result15
20 - - B -- OUTPUT 0 1 0 0 result16
86 - - B -- OUTPUT 0 1 0 0 result17
44 - - - 18 OUTPUT 0 1 0 0 result18
19 - - B -- OUTPUT 0 1 0 0 result19
46 - - - 17 OUTPUT 0 1 0 0 result20
21 - - B -- OUTPUT 0 1 0 0 result21
89 - - B -- OUTPUT 0 1 0 0 result22
49 - - - 14 OUTPUT 0 1 0 0 result23
30 - - C -- OUTPUT 0 1 0 0 result24
47 - - - 16 OUTPUT 0 1 0 0 result25
26 - - C -- OUTPUT 0 1 0 0 result26
33 - - C -- OUTPUT 0 1 0 0 result27
32 - - C -- OUTPUT 0 1 0 0 result28
135 - - - 18 OUTPUT 0 1 0 0 result29
29 - - C -- OUTPUT 0 1 0 0 result30
31 - - C -- OUTPUT 0 1 0 0 result31
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:g:\taoyuhui\synplifywork_new\statemachine_mult\rev_2\maxplus\st_mult1.rpt
st_mult1
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - C 23 OR2 1 2 0 1 bei_cheng_shu_Temp_1_i_m2_1_~7
- 1 - C 23 OR2 1 2 0 1 bei_cheng_shu_Temp_1_i_m2_2_~7
- 4 - C 13 OR2 1 2 0 1 bei_cheng_shu_Temp_1_i_m2_3_~7
- 6 - C 13 OR2 1 2 0 1 bei_cheng_shu_Temp_1_i_m2_4_~7
- 2 - A 14 OR2 1 2 0 1 bei_cheng_shu_Temp_1_i_m2_5_~7
- 5 - A 14 OR2 1 2 0 1 bei_cheng_shu_Temp_1_i_m2_6_~7
- 8 - A 14 OR2 1 2 0 1 bei_cheng_shu_Temp_1_i_m2_7_~7
- 4 - B 12 OR2 1 2 0 1 bei_cheng_shu_Temp_1_i_m2_8_~7
- 6 - B 12 OR2 1 2 0 1 bei_cheng_shu_Temp_1_i_m2_9_~7
- 8 - B 12 OR2 1 2 0 1 bei_cheng_shu_Temp_1_i_m2_10_~7
- 3 - B 03 OR2 1 2 0 1 bei_cheng_shu_Temp_1_i_m2_11_~7
- 6 - B 03 OR2 1 2 0 1 bei_cheng_shu_Temp_1_i_m2_12_~7
- 8 - B 03 OR2 1 2 0 1 bei_cheng_shu_Temp_1_i_m2_13_~7
- 1 - B 15 OR2 1 2 0 1 bei_cheng_shu_Temp_1_i_m2_14_~7
- 5 - B 23 OR2 1 2 0 1 bei_cheng_shu_Temp_1_i_m2_15_~7
- 8 - C 19 AND2 0 2 0 19 count18_0_a2~1
- 4 - B 15 DFFE + 1 1 0 41 current_state_0_ (current_state0)
- 2 - C 19 DFFE + 1 1 0 40 current_state_1_ (current_state1)
- 5 - C 23 OR2 1 2 0 2 |lpm_latch:bei_cheng_shu_Temp_0_|:49
- 7 - C 23 LCELL 0 2 0 2 |lpm_latch:bei_cheng_shu_Temp_1_|latches0
- 2 - C 13 LCELL 0 2 0 2 |lpm_latch:bei_cheng_shu_Temp_2_|latches0
- 5 - C 13 LCELL 0 2 0 2 |lpm_latch:bei_cheng_shu_Temp_3_|latches0
- 1 - C 13 LCELL 0 2 0 2 |lpm_latch:bei_cheng_shu_Temp_4_|latches0
- 3 - A 14 LCELL 0 2 0 2 |lpm_latch:bei_cheng_shu_Temp_5_|latches0
- 7 - A 14 LCELL 0 2 0 2 |lpm_latch:bei_cheng_shu_Temp_6_|latches0
- 6 - A 14 LCELL 0 2 0 2 |lpm_latch:bei_cheng_shu_Temp_7_|latches0
- 5 - B 12 LCELL 0 2 0 2 |lpm_latch:bei_cheng_shu_Temp_8_|latches0
- 7 - B 12 LCELL 0 2 0 2 |lpm_latch:bei_cheng_shu_Temp_9_|latches0
- 1 - B 12 LCELL 0 2 0 2 |lpm_latch:bei_cheng_shu_Temp_10_|latches0
- 5 - B 03 LCELL 0 2 0 2 |lpm_latch:bei_cheng_shu_Temp_11_|latches0
- 7 - B 03 LCELL 0 2 0 2 |lpm_latch:bei_cheng_shu_Temp_12_|latches0
- 1 - B 03 LCELL 0 2 0 2 |lpm_latch:bei_cheng_shu_Temp_13_|latches0
- 3 - B 23 LCELL 0 2 0 2 |lpm_latch:bei_cheng_shu_Temp_14_|latches0
- 6 - B 23 LCELL 0 2 0 2 |lpm_latch:bei_cheng_shu_Temp_15_|latches0
- 8 - B 23 OR2 0 3 0 2 |lpm_latch:bei_cheng_shu_Temp_16_|:49
- 2 - B 23 OR2 0 3 0 2 |lpm_latch:bei_cheng_shu_Temp_17_|:49
- 4 - B 17 OR2 0 3 0 2 |lpm_latch:bei_cheng_shu_Temp_18_|:49
- 3 - B 17 OR2 0 3 0 2 |lpm_latch:bei_cheng_shu_Temp_19_|:49
- 6 - B 17 OR2 0 3 0 2 |lpm_latch:bei_cheng_shu_Temp_20_|:49
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