📄 st_mult1.rpt
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- 5 - B 22 LCELL 0 2 0 2 |lpm_latch:Mcnd_Temp_13_|latches0
- 8 - B 22 LCELL 0 2 0 2 |lpm_latch:Mcnd_Temp_14_|latches0
- 3 - B 22 LCELL 0 2 0 2 |lpm_latch:Mcnd_Temp_15_|latches0
- 1 - B 06 LCELL 0 3 0 2 |lpm_latch:Mcnd_Temp_16_|latches0
- 4 - B 06 LCELL 0 3 0 2 |lpm_latch:Mcnd_Temp_17_|latches0
- 8 - B 06 LCELL 0 3 0 2 |lpm_latch:Mcnd_Temp_18_|latches0
- 3 - B 06 LCELL 0 3 0 2 |lpm_latch:Mcnd_Temp_19_|latches0
- 6 - B 06 LCELL 0 3 0 2 |lpm_latch:Mcnd_Temp_20_|latches0
- 5 - B 06 LCELL 0 3 0 2 |lpm_latch:Mcnd_Temp_21_|latches0
- 2 - B 06 LCELL 0 3 0 2 |lpm_latch:Mcnd_Temp_22_|latches0
- 7 - B 06 LCELL 0 3 0 2 |lpm_latch:Mcnd_Temp_23_|latches0
- 5 - B 04 LCELL 0 3 0 2 |lpm_latch:Mcnd_Temp_24_|latches0
- 4 - B 04 LCELL 0 3 0 2 |lpm_latch:Mcnd_Temp_25_|latches0
- 2 - B 04 LCELL 0 3 0 2 |lpm_latch:Mcnd_Temp_26_|latches0
- 8 - B 04 LCELL 0 3 0 2 |lpm_latch:Mcnd_Temp_27_|latches0
- 3 - B 04 LCELL 0 3 0 2 |lpm_latch:Mcnd_Temp_28_|latches0
- 7 - B 04 LCELL 0 3 0 2 |lpm_latch:Mcnd_Temp_29_|latches0
- 1 - B 04 LCELL 0 3 0 2 |lpm_latch:Mcnd_Temp_30_|latches0
- 6 - B 04 LCELL 0 3 0 1 |lpm_latch:Mcnd_Temp_31_|latches0
- 5 - A 22 OR2 0 3 0 2 |lpm_latch:state_temp_0_|:49
- 3 - B 21 OR2 0 3 0 1 |lpm_latch:state_temp_1_|:49
- 1 - B 09 OR2 1 3 0 1 Mcnd_Temp_1_1_~7
- 2 - B 09 OR2 1 3 0 1 Mcnd_Temp_1_2_~7
- 6 - B 09 OR2 1 3 0 1 Mcnd_Temp_1_3_~7
- 7 - B 09 OR2 1 3 0 1 Mcnd_Temp_1_4_~7
- 1 - B 18 OR2 1 3 0 1 Mcnd_Temp_1_5_~7
- 2 - B 18 OR2 1 3 0 1 Mcnd_Temp_1_6_~7
- 4 - B 18 OR2 1 3 0 1 Mcnd_Temp_1_7_~7
- 2 - B 11 OR2 1 3 0 1 Mcnd_Temp_1_8_~7
- 5 - B 11 OR2 1 3 0 1 Mcnd_Temp_1_9_~7
- 6 - B 11 OR2 1 3 0 1 Mcnd_Temp_1_10_~7
- 7 - B 11 OR2 1 3 0 1 Mcnd_Temp_1_11_~7
- 1 - B 22 OR2 1 3 0 1 Mcnd_Temp_1_12_~7
- 2 - B 22 OR2 1 3 0 1 Mcnd_Temp_1_13_~7
- 4 - B 22 OR2 1 3 0 1 Mcnd_Temp_1_14_~7
- 7 - B 22 OR2 1 3 0 1 Mcnd_Temp_1_15_~7
- 4 - A 22 DFFE + 1 1 0 86 Mpy_State_0_ (Mpy_State0)
- 2 - B 21 DFFE + 1 1 0 70 Mpy_State_1_ (Mpy_State1)
- 1 - A 19 LCELL 0 2 0 3 N_3_lx_0 (N_3_clc)
- 2 - A 19 LCELL 0 2 0 2 N_4_lx_0 (N_4_clc)
- 2 - A 16 LCELL 0 2 0 2 N_5_lx_0 (N_5_clc)
- 3 - A 16 LCELL 0 2 0 2 N_7_lx_0 (N_7_clc)
- 4 - A 19 LCELL 0 2 0 2 N_8_lx_0 (N_8_clc)
- 4 - A 16 LCELL 0 2 0 2 N_9_lx_0 (N_9_clc)
- 5 - A 19 LCELL 0 2 0 2 N_10_lx_0 (N_10_clc)
- 5 - A 16 LCELL 0 2 0 2 N_11_lx_0 (N_11_clc)
- 6 - A 19 LCELL 0 2 0 2 N_12_lx_0 (N_12_clc)
- 6 - A 16 LCELL 0 2 0 2 N_13_lx_0 (N_13_clc)
- 7 - A 19 LCELL 0 2 0 2 N_14_lx_0 (N_14_clc)
- 7 - A 16 LCELL 0 2 0 2 N_15_lx_0 (N_15_clc)
- 8 - A 19 LCELL 0 2 0 2 N_16_lx_0 (N_16_clc)
- 8 - A 16 LCELL 0 2 0 2 N_17_lx_0 (N_17_clc)
- 1 - A 21 LCELL 0 2 0 2 N_18_lx_0 (N_18_clc)
- 1 - A 18 LCELL 0 2 0 2 N_19_lx_0 (N_19_clc)
- 2 - A 21 LCELL 0 2 0 2 N_20_lx_0 (N_20_clc)
- 2 - A 18 LCELL 0 2 0 2 N_21_lx_0 (N_21_clc)
- 3 - A 21 LCELL 0 2 0 2 N_22_lx_0 (N_22_clc)
- 3 - A 18 LCELL 0 2 0 2 N_23_lx_0 (N_23_clc)
- 4 - A 21 LCELL 0 2 0 2 N_24_lx_0 (N_24_clc)
- 4 - A 18 LCELL 0 2 0 2 N_25_lx_0 (N_25_clc)
- 5 - A 21 LCELL 0 2 0 2 N_26_lx_0 (N_26_clc)
- 5 - A 18 LCELL 0 2 0 2 N_27_lx_0 (N_27_clc)
- 6 - A 21 LCELL 0 2 0 2 N_28_lx_0 (N_28_clc)
- 6 - A 18 LCELL 0 2 0 2 N_29_lx_0 (N_29_clc)
- 7 - A 21 LCELL 0 2 0 2 N_30_lx_0 (N_30_clc)
- 7 - A 18 LCELL 0 2 0 2 N_31_lx_0 (N_31_clc)
- 8 - A 21 LCELL 0 1 0 1 N_32_lx_0 (N_32_clc)
- 8 - A 18 LCELL 0 2 0 1 N_33_lx_0 (N_33_clc)
- 3 - A 19 LCELL 0 2 0 2 N_104_lx_0 (N_104_clc)
- 1 - B 21 AND2 0 2 0 32 state_temp_0_sqmuxa~1
- 2 - A 22 OR2 0 4 0 1 state_temp_1_sqmuxa_1_0~8
- 3 - A 22 OR2 0 4 0 1 state_temp_1_0_~9
- 3 - A 14 CASCADE 2 2 0 1 N_26 (state_temp11_3_0_cas)
- 5 - A 14 CASCADE 2 2 0 1 N_28 (state_temp11_6_0_cas)
- 1 - C 20 CASCADE 2 2 0 1 N_24 (state_temp11_10_0_cas)
- 1 - A 14 CASCADE 2 2 0 1 N_22 (state_temp11_13_0_cas)
- 7 - A 14 CASCADE 0 4 0 1 N_20 (state_temp11_15_0_cas)
- 3 - A 15 CASCADE 0 2 0 1 N_18 (state_temp26_4_cas)
- 4 - A 15 CASCADE 0 5 0 1 N_16 (state_temp26_8_cas)
- 5 - A 15 CASCADE 0 5 0 1 N_14 (state_temp26_12_cas)
- 6 - A 15 CASCADE 0 5 0 1 N_12 (state_temp26_16_cas)
- 7 - A 15 CASCADE 0 5 0 1 N_10 (state_temp26_20_cas)
- 8 - A 15 CASCADE 0 5 0 1 N_8 (state_temp26_24_cas)
- 1 - A 17 CASCADE 0 5 0 1 N_6 (state_temp26_28_cas)
- 1 - B 01 LCELL 0 2 0 1 un4_Acc_add0_lx_0 (un4_Acc_add0_clc)
- 2 - B 01 LCELL 0 2 0 1 un4_Acc_add1_lx_0 (un4_Acc_add1_clc)
- 3 - B 01 LCELL 0 2 0 1 un4_Acc_add2_lx_0 (un4_Acc_add2_clc)
- 4 - B 01 LCELL 0 2 0 1 un4_Acc_add3_lx_0 (un4_Acc_add3_clc)
- 5 - B 01 LCELL 0 2 0 1 un4_Acc_add4_lx_0 (un4_Acc_add4_clc)
- 6 - B 01 LCELL 0 2 0 1 un4_Acc_add5_lx_0 (un4_Acc_add5_clc)
- 7 - B 01 LCELL 0 2 0 1 un4_Acc_add6_lx_0 (un4_Acc_add6_clc)
- 8 - B 01 LCELL 0 2 0 1 un4_Acc_add7_lx_0 (un4_Acc_add7_clc)
- 1 - B 03 LCELL 0 2 0 1 un4_Acc_add8_lx_0 (un4_Acc_add8_clc)
- 2 - B 03 LCELL 0 2 0 1 un4_Acc_add9_lx_0 (un4_Acc_add9_clc)
- 3 - B 03 LCELL 0 2 0 1 un4_Acc_add10_lx_0 (un4_Acc_add10_clc)
- 4 - B 03 LCELL 0 2 0 1 un4_Acc_add11_lx_0 (un4_Acc_add11_clc)
- 5 - B 03 LCELL 0 2 0 1 un4_Acc_add12_lx_0 (un4_Acc_add12_clc)
- 6 - B 03 LCELL 0 2 0 1 un4_Acc_add13_lx_0 (un4_Acc_add13_clc)
- 7 - B 03 LCELL 0 2 0 1 un4_Acc_add14_lx_0 (un4_Acc_add14_clc)
- 8 - B 03 LCELL 0 2 0 1 un4_Acc_add15_lx_0 (un4_Acc_add15_clc)
- 1 - B 05 LCELL 0 2 0 1 un4_Acc_add16_lx_0 (un4_Acc_add16_clc)
- 2 - B 05 LCELL 0 2 0 1 un4_Acc_add17_lx_0 (un4_Acc_add17_clc)
- 3 - B 05 LCELL 0 2 0 1 un4_Acc_add18_lx_0 (un4_Acc_add18_clc)
- 4 - B 05 LCELL 0 2 0 1 un4_Acc_add19_lx_0 (un4_Acc_add19_clc)
- 5 - B 05 LCELL 0 2 0 1 un4_Acc_add20_lx_0 (un4_Acc_add20_clc)
- 6 - B 05 LCELL 0 2 0 1 un4_Acc_add21_lx_0 (un4_Acc_add21_clc)
- 7 - B 05 LCELL 0 2 0 1 un4_Acc_add22_lx_0 (un4_Acc_add22_clc)
- 8 - B 05 LCELL 0 2 0 1 un4_Acc_add23_lx_0 (un4_Acc_add23_clc)
- 1 - B 07 LCELL 0 2 0 1 un4_Acc_add24_lx_0 (un4_Acc_add24_clc)
- 2 - B 07 LCELL 0 2 0 1 un4_Acc_add25_lx_0 (un4_Acc_add25_clc)
- 3 - B 07 LCELL 0 2 0 1 un4_Acc_add26_lx_0 (un4_Acc_add26_clc)
- 4 - B 07 LCELL 0 2 0 1 un4_Acc_add27_lx_0 (un4_Acc_add27_clc)
- 5 - B 07 LCELL 0 2 0 1 un4_Acc_add28_lx_0 (un4_Acc_add28_clc)
- 6 - B 07 LCELL 0 2 0 1 un4_Acc_add29_lx_0 (un4_Acc_add29_clc)
- 7 - B 07 LCELL 0 2 0 1 un4_Acc_add30_lx_0 (un4_Acc_add30_clc)
- 8 - B 07 LCELL 0 2 0 1 un4_Acc_add31 (:293)
- 2 - A 17 LCELL 0 5 0 2 state_temp26_28 (:300)
- 8 - A 14 LCELL 0 5 0 3 state_temp11_15_0 (:315)
- 2 - A 14 LCELL 2 3 0 1 state_temp11_13_0 (:318)
- 2 - C 20 LCELL 2 3 0 1 state_temp11_10_0 (:321)
- 4 - A 14 LCELL 2 3 0 1 state_temp11_3_0 (:324)
- 6 - A 14 LCELL 2 3 0 1 state_temp11_6_0 (:327)
- 1 - A 16 CARRY 0 2 0 1 |carry_sum:N_3_cry|:31
- 2 - A 19 CARRY 0 3 0 1 |carry_sum:N_4_cry|:31
- 2 - A 16 CARRY 0 3 0 1 |carry_sum:N_5_cry|:31
- 3 - A 16 CARRY 0 3 0 1 |carry_sum:N_7_cry|:31
- 4 - A 19 CARRY 0 3 0 1 |carry_sum:N_8_cry|:31
- 4 - A 16 CARRY 0 3 0 1 |carry_sum:N_9_cry|:31
- 5 - A 19 CARRY 0 3 0 1 |carry_sum:N_10_cry|:31
- 5 - A 16 CARRY 0 3 0 1 |carry_sum:N_11_cry|:31
- 6 - A 19 CARRY 0 3 0 1 |carry_sum:N_12_cry|:31
- 6 - A 16 CARRY 0 3 0 1 |carry_sum:N_13_cry|:31
- 7 - A 19 CARRY 0 3 0 1 |carry_sum:N_14_cry|:31
- 7 - A 16 CARRY 0 3 0 1 |carry_sum:N_15_cry|:31
- 8 - A 19 CARRY 0 3 0 1 |carry_sum:N_16_cry|:31
- 8 - A 16 CARRY 0 3 0 1 |carry_sum:N_17_cry|:31
- 1 - A 21 CARRY 0 3 0 1 |carry_sum:N_18_cry|:31
- 1 - A 18 CARRY 0 3 0 1 |carry_sum:N_19_cry|:31
- 2 - A 21 CARRY 0 3 0 1 |carry_sum:N_20_cry|:31
- 2 - A 18 CARRY 0 3 0 1 |carry_sum:N_21_cry|:31
- 3 - A 21 CARRY 0 3 0 1 |carry_sum:N_22_cry|:31
- 3 - A 18 CARRY 0 3 0 1 |carry_sum:N_23_cry|:31
- 4 - A 21 CARRY 0 3 0 1 |carry_sum:N_24_cry|:31
- 4 - A 18 CARRY 0 3 0 1 |carry_sum:N_25_cry|:31
- 5 - A 21 CARRY 0 3 0 1 |carry_sum:N_26_cry|:31
- 5 - A 18 CARRY 0 3 0 1 |carry_sum:N_27_cry|:31
- 6 - A 21 CARRY 0 3 0 1 |carry_sum:N_28_cry|:31
- 6 - A 18 CARRY 0 3 0 1 |carry_sum:N_29_cry|:31
- 7 - A 21 CARRY 0 3 0 1 |carry_sum:N_30_cry|:31
- 7 - A 18 CARRY 0 3 0 1 |carry_sum:N_31_cry|:31
- 8 - A 21 CARRY 0 2 0 1 |carry_sum:N_32_cry|:31
- 8 - A 18 CARRY 0 3 0 1 |carry_sum:N_33_cry|:31
- 3 - A 19 CARRY 0 3 0 1 |carry_sum:N_104_cry|:31
- 1 - B 01 CARRY 0 2 0 1 |carry_sum:un4_Acc_add0_cry|:31
- 2 - B 01 CARRY 0 3 0 1 |carry_sum:un4_Acc_add1_cry|:31
- 3 - B 01 CARRY 0 3 0 1 |carry_sum:un4_Acc_add2_cry|:31
- 4 - B 01 CARRY 0 3 0 1 |carry_sum:un4_Acc_add3_cry|:31
- 5 - B 01 CARRY 0 3 0 1 |carry_sum:un4_Acc_add4_cry|:31
- 6 - B 01 CARRY 0 3 0 1 |carry_sum:un4_Acc_add5_cry|:31
- 7 - B 01 CARRY 0 3 0 1 |carry_sum:un4_Acc_add6_cry|:31
- 8 - B 01 CARRY 0 3 0 1 |carry_sum:un4_Acc_add7_cry|:31
- 1 - B 03 CARRY 0 3 0 1 |carry_sum:un4_Acc_add8_cry|:31
- 2 - B 03 CARRY 0 3 0 1 |carry_sum:un4_Acc_add9_cry|:31
- 3 - B 03 CARRY 0 3 0 1 |carry_sum:un4_Acc_add10_cry|:31
- 4 - B 03 CARRY 0 3 0 1 |carry_sum:un4_Acc_add11_cry|:31
- 5 - B 03 CARRY 0 3 0 1 |carry_sum:un4_Acc_add12_cry|:31
- 6 - B 03 CARRY 0 3 0 1 |carry_sum:un4_Acc_add13_cry|:31
- 7 - B 03 CARRY 0 3 0 1 |carry_sum:un4_Acc_add14_cry|:31
- 8 - B 03 CARRY 0 3 0 1 |carry_sum:un4_Acc_add15_cry|:31
- 1 - B 05 CARRY 0 3 0 1 |carry_sum:un4_Acc_add16_cry|:31
- 2 - B 05 CARRY 0 3 0 1 |carry_sum:un4_Acc_add17_cry|:31
- 3 - B 05 CARRY 0 3 0 1 |carry_sum:un4_Acc_add18_cry|:31
- 4 - B 05 CARRY 0 3 0 1 |carry_sum:un4_Acc_add19_cry|:31
- 5 - B 05 CARRY 0 3 0 1 |carry_sum:un4_Acc_add20_cry|:31
- 6 - B 05 CARRY 0 3 0 1 |carry_sum:un4_Acc_add21_cry|:31
- 7 - B 05 CARRY 0 3 0 1 |carry_sum:un4_Acc_add22_cry|:31
- 8 - B 05 CARRY 0 3 0 1 |carry_sum:un4_Acc_add23_cry|:31
- 1 - B 07 CARRY 0 3 0 1 |carry_sum:un4_Acc_add24_cry|:31
- 2 - B 07 CARRY 0 3 0 1 |carry_sum:un4_Acc_add25_cry|:31
- 3 - B 07 CARRY 0 3 0 1 |carry_sum:un4_Acc_add26_cry|:31
- 4 - B 07 CARRY 0 3 0 1 |carry_sum:un4_Acc_add27_cry|:31
- 5 - B 07 CARRY 0 3 0 1 |carry_sum:un4_Acc_add28_cry|:31
- 6 - B 07 CARRY 0 3 0 1 |carry_sum:un4_Acc_add29_cry|:31
- 7 - B 07 CARRY 0 3 0 1 |carry_sum:un4_Acc_add30_cry|:31
- 1 - A 19 CARRY 0 2 0 1 un3_Count_COUT_0_ (un3_Count_cry_0_)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:g:\taoyuhui\synplifywork_new\statemachine_mult\rev_2\st_mult1.rpt
st_mult1
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
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