📄 st_mult1.rpt
字号:
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 2 0 1 1 0 6/0
Total: 9 9 9 9 9 9 9 9 9 9 9 9 0 3 8 6 8 8 17 8 5 11 17 4 2 205/0
Device-Specific Information:g:\taoyuhui\synplifywork_new\statemachine_mult\rev_2\st_mult1.rpt
st_mult1
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
55 - - - -- INPUT G 0 0 0 0 Clock
56 - - - -- INPUT 0 0 0 1 Mcnd0
124 - - - -- INPUT 0 0 0 1 Mcnd1
126 - - - -- INPUT 0 0 0 1 Mcnd2
125 - - - -- INPUT 0 0 0 1 Mcnd3
116 - - - 05 INPUT 0 0 0 1 Mcnd4
131 - - - 15 INPUT 0 0 0 1 Mcnd5
137 - - - 19 INPUT 0 0 0 1 Mcnd6
133 - - - 17 INPUT 0 0 0 1 Mcnd7
113 - - - 03 INPUT 0 0 0 1 Mcnd8
72 - - - 04 INPUT 0 0 0 1 Mcnd9
117 - - - 06 INPUT 0 0 0 1 Mcnd10
18 - - B -- INPUT 0 0 0 1 Mcnd11
20 - - B -- INPUT 0 0 0 1 Mcnd12
48 - - - 15 INPUT 0 0 0 1 Mcnd13
39 - - - 21 INPUT 0 0 0 1 Mcnd14
91 - - B -- INPUT 0 0 0 1 Mcnd15
99 - - A -- INPUT 0 0 0 1 Mplr0
81 - - C -- INPUT 0 0 0 1 Mplr1
14 - - A -- INPUT 0 0 0 1 Mplr2
9 - - A -- INPUT 0 0 0 1 Mplr3
102 - - A -- INPUT 0 0 0 1 Mplr4
29 - - C -- INPUT 0 0 0 1 Mplr5
8 - - A -- INPUT 0 0 0 1 Mplr6
11 - - A -- INPUT 0 0 0 1 Mplr7
13 - - A -- INPUT 0 0 0 1 Mplr8
82 - - C -- INPUT 0 0 0 1 Mplr9
10 - - A -- INPUT 0 0 0 1 Mplr10
97 - - A -- INPUT 0 0 0 1 Mplr11
96 - - A -- INPUT 0 0 0 1 Mplr12
83 - - C -- INPUT 0 0 0 1 Mplr13
101 - - A -- INPUT 0 0 0 1 Mplr14
100 - - A -- INPUT 0 0 0 1 Mplr15
54 - - - -- INPUT 0 0 0 2 Reset
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information:g:\taoyuhui\synplifywork_new\statemachine_mult\rev_2\st_mult1.rpt
st_mult1
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
120 - - - 09 OUTPUT 0 1 0 0 Acc0
17 - - B -- OUTPUT 0 1 0 0 Acc1
23 - - B -- OUTPUT 0 1 0 0 Acc2
73 - - - 02 OUTPUT 0 1 0 0 Acc3
60 - - - 12 OUTPUT 0 1 0 0 Acc4
119 - - - 08 OUTPUT 0 1 0 0 Acc5
64 - - - 10 OUTPUT 0 1 0 0 Acc6
92 - - B -- OUTPUT 0 1 0 0 Acc7
109 - - - 01 OUTPUT 0 1 0 0 Acc8
80 - - C -- OUTPUT 0 1 0 0 Acc9
59 - - - 12 OUTPUT 0 1 0 0 Acc10
122 - - - 12 OUTPUT 0 1 0 0 Acc11
90 - - B -- OUTPUT 0 1 0 0 Acc12
121 - - - 10 OUTPUT 0 1 0 0 Acc13
22 - - B -- OUTPUT 0 1 0 0 Acc14
19 - - B -- OUTPUT 0 1 0 0 Acc15
65 - - - 09 OUTPUT 0 1 0 0 Acc16
68 - - - 07 OUTPUT 0 1 0 0 Acc17
21 - - B -- OUTPUT 0 1 0 0 Acc18
31 - - C -- OUTPUT 0 1 0 0 Acc19
110 - - - 01 OUTPUT 0 1 0 0 Acc20
78 - - C -- OUTPUT 0 1 0 0 Acc21
89 - - B -- OUTPUT 0 1 0 0 Acc22
95 - - A -- OUTPUT 0 1 0 0 Acc23
63 - - - 11 OUTPUT 0 1 0 0 Acc24
87 - - B -- OUTPUT 0 1 0 0 Acc25
111 - - - 02 OUTPUT 0 1 0 0 Acc26
88 - - B -- OUTPUT 0 1 0 0 Acc27
118 - - - 07 OUTPUT 0 1 0 0 Acc28
33 - - C -- OUTPUT 0 1 0 0 Acc29
67 - - - 08 OUTPUT 0 1 0 0 Acc30
86 - - B -- OUTPUT 0 1 0 0 Acc31
7 - - A -- OUTPUT 0 1 0 0 Done
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:g:\taoyuhui\synplifywork_new\statemachine_mult\rev_2\st_mult1.rpt
st_mult1
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - A 23 LCELL 0 2 0 1 Count_1_30_ (Count_1_30)
- 1 - A 20 LCELL 0 2 0 1 Count_1_31_ (Count_1_31)
- 8 - B 18 OR2 ! 0 2 0 32 Count11~1
- 6 - A 22 OR2 0 4 0 1 Done_1~11
- 4 - B 10 OR2 0 3 1 1 |lpm_latch:Acc_0_|:49
- 1 - B 02 OR2 0 3 1 1 |lpm_latch:Acc_1_|:49
- 7 - B 08 OR2 0 3 1 1 |lpm_latch:Acc_2_|:49
- 3 - B 02 OR2 0 3 1 1 |lpm_latch:Acc_3_|:49
- 4 - B 12 OR2 0 3 1 1 |lpm_latch:Acc_4_|:49
- 8 - B 08 OR2 0 3 1 1 |lpm_latch:Acc_5_|:49
- 5 - B 10 OR2 0 3 1 1 |lpm_latch:Acc_6_|:49
- 4 - B 08 OR2 0 3 1 1 |lpm_latch:Acc_7_|:49
- 8 - B 02 OR2 0 3 1 1 |lpm_latch:Acc_8_|:49
- 3 - B 10 OR2 0 3 1 1 |lpm_latch:Acc_9_|:49
- 2 - B 12 OR2 0 3 1 1 |lpm_latch:Acc_10_|:49
- 3 - B 12 OR2 0 3 1 1 |lpm_latch:Acc_11_|:49
- 4 - B 02 OR2 0 3 1 1 |lpm_latch:Acc_12_|:49
- 2 - B 10 OR2 0 3 1 1 |lpm_latch:Acc_13_|:49
- 5 - B 02 OR2 0 3 1 1 |lpm_latch:Acc_14_|:49
- 2 - B 08 OR2 0 3 1 1 |lpm_latch:Acc_15_|:49
- 1 - B 10 OR2 0 3 1 1 |lpm_latch:Acc_16_|:49
- 3 - B 08 OR2 0 3 1 1 |lpm_latch:Acc_17_|:49
- 5 - B 08 OR2 0 3 1 1 |lpm_latch:Acc_18_|:49
- 6 - B 10 OR2 0 3 1 1 |lpm_latch:Acc_19_|:49
- 6 - B 02 OR2 0 3 1 1 |lpm_latch:Acc_20_|:49
- 7 - B 10 OR2 0 3 1 1 |lpm_latch:Acc_21_|:49
- 8 - B 12 OR2 0 3 1 1 |lpm_latch:Acc_22_|:49
- 8 - B 10 OR2 0 3 1 1 |lpm_latch:Acc_23_|:49
- 1 - B 12 OR2 0 3 1 1 |lpm_latch:Acc_24_|:49
- 6 - B 12 OR2 0 3 1 1 |lpm_latch:Acc_25_|:49
- 2 - B 02 OR2 0 3 1 1 |lpm_latch:Acc_26_|:49
- 5 - B 12 OR2 0 3 1 1 |lpm_latch:Acc_27_|:49
- 1 - B 08 OR2 0 3 1 1 |lpm_latch:Acc_28_|:49
- 7 - B 02 OR2 0 3 1 1 |lpm_latch:Acc_29_|:49
- 6 - B 08 OR2 0 3 1 1 |lpm_latch:Acc_30_|:49
- 7 - B 12 OR2 0 3 1 1 |lpm_latch:Acc_31_|:49
- 8 - A 22 LCELL 0 2 0 6 |lpm_latch:Count_0_|latches0
- 7 - A 22 LCELL 0 3 0 4 |lpm_latch:Count_1_|latches0
- 1 - C 18 LCELL 0 3 0 10 |lpm_latch:Count_2_|latches0
- 2 - C 22 LCELL 0 3 0 10 |lpm_latch:Count_3_|latches0
- 2 - C 13 LCELL 0 3 0 2 |lpm_latch:Count_4_|latches0
- 5 - A 17 LCELL 0 3 0 2 |lpm_latch:Count_5_|latches0
- 7 - A 17 LCELL 0 3 0 2 |lpm_latch:Count_6_|latches0
- 3 - A 17 LCELL 0 3 0 2 |lpm_latch:Count_7_|latches0
- 8 - A 17 LCELL 0 3 0 2 |lpm_latch:Count_8_|latches0
- 4 - A 17 LCELL 0 3 0 2 |lpm_latch:Count_9_|latches0
- 6 - A 17 LCELL 0 3 0 2 |lpm_latch:Count_10_|latches0
- 7 - B 24 LCELL 0 3 0 2 |lpm_latch:Count_11_|latches0
- 4 - B 13 LCELL 0 3 0 2 |lpm_latch:Count_12_|latches0
- 1 - A 03 LCELL 0 3 0 2 |lpm_latch:Count_13_|latches0
- 4 - A 05 LCELL 0 3 0 2 |lpm_latch:Count_14_|latches0
- 2 - A 08 LCELL 0 3 0 2 |lpm_latch:Count_15_|latches0
- 2 - C 23 LCELL 0 3 0 2 |lpm_latch:Count_16_|latches0
- 2 - A 12 LCELL 0 3 0 2 |lpm_latch:Count_17_|latches0
- 5 - A 09 LCELL 0 3 0 2 |lpm_latch:Count_18_|latches0
- 1 - B 20 LCELL 0 3 0 2 |lpm_latch:Count_19_|latches0
- 2 - A 02 LCELL 0 3 0 2 |lpm_latch:Count_20_|latches0
- 2 - A 06 LCELL 0 3 0 2 |lpm_latch:Count_21_|latches0
- 2 - A 07 LCELL 0 3 0 2 |lpm_latch:Count_22_|latches0
- 2 - A 11 LCELL 0 3 0 2 |lpm_latch:Count_23_|latches0
- 8 - A 24 LCELL 0 3 0 2 |lpm_latch:Count_24_|latches0
- 1 - A 01 LCELL 0 3 0 2 |lpm_latch:Count_25_|latches0
- 4 - B 23 LCELL 0 3 0 2 |lpm_latch:Count_26_|latches0
- 1 - A 13 LCELL 0 3 0 2 |lpm_latch:Count_27_|latches0
- 2 - A 04 LCELL 0 3 0 2 |lpm_latch:Count_28_|latches0
- 8 - A 10 LCELL 0 3 0 2 |lpm_latch:Count_29_|latches0
- 3 - A 23 LCELL 0 2 0 2 |lpm_latch:Count_30_|latches0
- 6 - A 20 LCELL 0 2 0 1 |lpm_latch:Count_31_|latches0
- 1 - A 22 OR2 0 3 1 1 |lpm_latch:Done1|:49
- 5 - B 09 LCELL 1 2 0 2 |lpm_latch:Mcnd_Temp_0_|latches0
- 8 - B 09 LCELL 0 2 0 2 |lpm_latch:Mcnd_Temp_1_|latches0
- 4 - B 09 LCELL 0 2 0 2 |lpm_latch:Mcnd_Temp_2_|latches0
- 3 - B 09 LCELL 0 2 0 2 |lpm_latch:Mcnd_Temp_3_|latches0
- 5 - B 18 LCELL 0 2 0 2 |lpm_latch:Mcnd_Temp_4_|latches0
- 3 - B 18 LCELL 0 2 0 2 |lpm_latch:Mcnd_Temp_5_|latches0
- 6 - B 18 LCELL 0 2 0 2 |lpm_latch:Mcnd_Temp_6_|latches0
- 7 - B 18 LCELL 0 2 0 2 |lpm_latch:Mcnd_Temp_7_|latches0
- 1 - B 11 LCELL 0 2 0 2 |lpm_latch:Mcnd_Temp_8_|latches0
- 4 - B 11 LCELL 0 2 0 2 |lpm_latch:Mcnd_Temp_9_|latches0
- 8 - B 11 LCELL 0 2 0 2 |lpm_latch:Mcnd_Temp_10_|latches0
- 3 - B 11 LCELL 0 2 0 2 |lpm_latch:Mcnd_Temp_11_|latches0
- 6 - B 22 LCELL 0 2 0 2 |lpm_latch:Mcnd_Temp_12_|latches0
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