📄 st_mult1.rpt
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|carry_sum:N_30_cry|
|carry_sum:N_31_cry|
|carry_sum:N_32_cry|
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Device-Specific Information:g:\taoyuhui\synplifywork_new\statemachine_mult\rev_2\st_mult1.rpt
st_mult1
***** Logic for device 'st_mult1' compiled without errors.
Device: EPF10K10TC144-3
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
R R R R R R R R R R R R R
E E E E E E E E E E E E E
S S S S S S S S S S S G V M S S
E E E E E G E M E E V M E M E G E N M M M C A A A c M V E M E A A
R R R R R N R c R R C c R c R N R D c c c C c c A A c n c C R c R c c A
V V V V V D V n V V C n V n V D V I n n n I c c c c c d n C V n V c c c
E E E E E I E d E E I d E d E I E N d d d N 1 1 c c 2 1 d I E d E 2 2 c
D D D D D O D 6 D D O 7 D 5 D O D T 2 3 1 T 1 3 0 5 8 0 4 O D 8 D 6 0 8
--------------------------------------------------------------------------_
/ 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 |_
/ 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 |
#TCK | 1 108 | ^DATA0
^CONF_DONE | 2 107 | ^DCLK
^nCEO | 3 106 | ^nCE
#TDO | 4 105 | #TDI
VCCIO | 5 104 | GNDIO
VCCINT | 6 103 | GNDINT
Done | 7 102 | Mplr4
Mplr6 | 8 101 | Mplr14
Mplr3 | 9 100 | Mplr15
Mplr10 | 10 99 | Mplr0
Mplr7 | 11 98 | RESERVED
RESERVED | 12 97 | Mplr11
Mplr8 | 13 96 | Mplr12
Mplr2 | 14 95 | Acc23
GNDIO | 15 94 | VCCIO
GNDINT | 16 93 | VCCINT
Acc1 | 17 92 | Acc7
Mcnd11 | 18 91 | Mcnd15
Acc15 | 19 EPF10K10TC144-3 90 | Acc12
Mcnd12 | 20 89 | Acc22
Acc18 | 21 88 | Acc27
Acc14 | 22 87 | Acc25
Acc2 | 23 86 | Acc31
VCCIO | 24 85 | GNDIO
VCCINT | 25 84 | GNDINT
RESERVED | 26 83 | Mplr13
RESERVED | 27 82 | Mplr9
RESERVED | 28 81 | Mplr1
Mplr5 | 29 80 | Acc9
RESERVED | 30 79 | RESERVED
Acc19 | 31 78 | Acc21
RESERVED | 32 77 | ^MSEL0
Acc29 | 33 76 | ^MSEL1
#TMS | 34 75 | VCCINT
^nSTATUS | 35 74 | ^nCONFIG
RESERVED | 36 73 | Acc3
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
R R M G R R R R V R R M R G R V V R C M G G A A V R A A A G A A R R V M
E E c N E E E E C E E c E N E C C e l c N N c c C E c c c N c c E E C c
S S n D S S S S C S S n S D S C C s o n D D c c C S c c c D c c S S C n
E E d I E E E E I E E d E I E I I e c d I I 1 4 I E 2 6 1 I 3 1 E E I d
R R 1 O R R R R O R R 1 R O R N N t k 0 N N 0 O R 4 6 O 0 7 R R O 9
V V 4 V V V V V V 3 V V T T T T V V V
E E E E E E E E E E E E E
D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information:g:\taoyuhui\synplifywork_new\statemachine_mult\rev_2\st_mult1.rpt
st_mult1
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A1 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
A2 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
A3 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
A4 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
A5 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
A6 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
A7 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
A8 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
A9 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
A10 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
A11 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
A12 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
A13 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
A14 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 17/22( 77%)
A15 6/ 8( 75%) 0/ 8( 0%) 0/ 8( 0%) 0/2 0/2 22/22(100%)
A16 8/ 8(100%) 2/ 8( 25%) 7/ 8( 87%) 0/2 0/2 16/22( 72%)
A17 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 0/2 0/2 10/22( 45%)
A18 8/ 8(100%) 1/ 8( 12%) 8/ 8(100%) 0/2 0/2 16/22( 72%)
A19 8/ 8(100%) 3/ 8( 37%) 8/ 8(100%) 0/2 0/2 16/22( 72%)
A20 2/ 8( 25%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
A21 8/ 8(100%) 3/ 8( 37%) 8/ 8(100%) 0/2 0/2 15/22( 68%)
A22 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 5/22( 22%)
A23 2/ 8( 25%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
A24 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
B1 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 0/2 0/2 16/22( 72%)
B2 8/ 8(100%) 5/ 8( 62%) 8/ 8(100%) 0/2 0/2 10/22( 45%)
B3 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 0/2 0/2 16/22( 72%)
B4 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 0/2 0/2 3/22( 13%)
B5 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 0/2 0/2 16/22( 72%)
B6 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 0/2 0/2 3/22( 13%)
B7 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 0/2 0/2 16/22( 72%)
B8 8/ 8(100%) 4/ 8( 50%) 8/ 8(100%) 0/2 0/2 10/22( 45%)
B9 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 7/22( 31%)
B10 8/ 8(100%) 8/ 8(100%) 8/ 8(100%) 0/2 0/2 10/22( 45%)
B11 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 7/22( 31%)
B12 8/ 8(100%) 4/ 8( 50%) 8/ 8(100%) 0/2 0/2 10/22( 45%)
B13 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
B18 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 6/22( 27%)
B20 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
B21 3/ 8( 37%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 3/22( 13%)
B22 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 7/22( 31%)
B23 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
B24 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
C13 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
C18 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
C20 2/ 8( 25%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 6/22( 27%)
C22 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
C23 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 61/96 ( 63%)
Total logic cells used: 205/576 ( 35%)
Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 3.21/4 ( 80%)
Total fan-in: 659/2304 ( 28%)
Total input pins required: 34
Total input I/O cell registers required: 0
Total output pins required: 33
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 205
Total flipflops required: 2
Total packed registers required: 0
Total logic cells in carry chains: 66
Total number of carry chains: 3
Total number of carry chains of length 1-8 : 0
Total number of carry chains of length 9-16: 0
Total number of carry chains of length 17-24: 2
Total number of carry chains of length 25-32: 1
Total logic cells in cascade chains: 18
Total number of cascade chains: 6
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 0/ 576 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 1 1 1 1 1 1 1 1 1 1 1 1 0 1 8 6 8 8 8 8 2 8 8 2 1 80/0
B: 8 8 8 8 8 8 8 8 8 8 8 8 0 1 0 0 0 0 8 0 1 3 8 1 1 119/0
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