st_mult1.tlg

veilog实现的状态机乘法器.可以参考

Selecting top level module st_mult1
@N:"G:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":1:7:1:14|Synthesizing module st_mult1

@W: CL118 :"G:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":26:1:26:4|Latch generated from always block for signal state_temp[1:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"G:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":26:1:26:4|Latch generated from always block for signal count[31:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"G:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":26:1:26:4|Latch generated from always block for signal bei_cheng_shu_Temp[31:0], probably caused by a missing assignment in an if or case stmt