st_mult1.srr

veilog实现的状态机乘法器.可以参考

	net "count[17]" in work.st_mult1(verilog)
	net "count[18]" in work.st_mult1(verilog)
	net "count[19]" in work.st_mult1(verilog)
	net "count[20]" in work.st_mult1(verilog)
	net "count[21]" in work.st_mult1(verilog)
	net "count[22]" in work.st_mult1(verilog)
	net "count[23]" in work.st_mult1(verilog)
	net "count[24]" in work.st_mult1(verilog)
	net "count[25]" in work.st_mult1(verilog)
	net "count[26]" in work.st_mult1(verilog)
	net "count[27]" in work.st_mult1(verilog)
	net "count[28]" in work.st_mult1(verilog)
	net "count[29]" in work.st_mult1(verilog)
	net "count[30]" in work.st_mult1(verilog)
	net "count[31]" in work.st_mult1(verilog)
	net "VCC" in work.st_mult1(verilog)
@W: BN137 :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":52:12:52:19|Found combinational loop during mapping at net un9_count[30]
31) instance work.st_mult1(verilog)-un9_count[31:0], output net "un9_count[30]" in work.st_mult1(verilog)
    input nets to instance:
	net "N_1" in work.st_mult1(verilog)
	net "count[1]" in work.st_mult1(verilog)
	net "count[2]" in work.st_mult1(verilog)
	net "count[3]" in work.st_mult1(verilog)
	net "N_5" in work.st_mult1(verilog)
	net "count[5]" in work.st_mult1(verilog)
	net "count[6]" in work.st_mult1(verilog)
	net "count[7]" in work.st_mult1(verilog)
	net "count[8]" in work.st_mult1(verilog)
	net "count[9]" in work.st_mult1(verilog)
	net "count[10]" in work.st_mult1(verilog)
	net "count[11]" in work.st_mult1(verilog)
	net "count[12]" in work.st_mult1(verilog)
	net "count[13]" in work.st_mult1(verilog)
	net "count[14]" in work.st_mult1(verilog)
	net "count[15]" in work.st_mult1(verilog)
	net "count[16]" in work.st_mult1(verilog)
	net "count[17]" in work.st_mult1(verilog)
	net "count[18]" in work.st_mult1(verilog)
	net "count[19]" in work.st_mult1(verilog)
	net "count[20]" in work.st_mult1(verilog)
	net "count[21]" in work.st_mult1(verilog)
	net "count[22]" in work.st_mult1(verilog)
	net "count[23]" in work.st_mult1(verilog)
	net "count[24]" in work.st_mult1(verilog)
	net "count[25]" in work.st_mult1(verilog)
	net "count[26]" in work.st_mult1(verilog)
	net "count[27]" in work.st_mult1(verilog)
	net "count[28]" in work.st_mult1(verilog)
	net "count[29]" in work.st_mult1(verilog)
	net "count[30]" in work.st_mult1(verilog)
	net "count[31]" in work.st_mult1(verilog)
	net "VCC" in work.st_mult1(verilog)
@W: BN137 :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":52:12:52:19|Found combinational loop during mapping at net un9_count[31]
32) instance work.st_mult1(verilog)-un9_count[31:0], output net "un9_count[31]" in work.st_mult1(verilog)
    input nets to instance:
	net "N_1" in work.st_mult1(verilog)
	net "count[1]" in work.st_mult1(verilog)
	net "count[2]" in work.st_mult1(verilog)
	net "count[3]" in work.st_mult1(verilog)
	net "N_5" in work.st_mult1(verilog)
	net "count[5]" in work.st_mult1(verilog)
	net "count[6]" in work.st_mult1(verilog)
	net "count[7]" in work.st_mult1(verilog)
	net "count[8]" in work.st_mult1(verilog)
	net "count[9]" in work.st_mult1(verilog)
	net "count[10]" in work.st_mult1(verilog)
	net "count[11]" in work.st_mult1(verilog)
	net "count[12]" in work.st_mult1(verilog)
	net "count[13]" in work.st_mult1(verilog)
	net "count[14]" in work.st_mult1(verilog)
	net "count[15]" in work.st_mult1(verilog)
	net "count[16]" in work.st_mult1(verilog)
	net "count[17]" in work.st_mult1(verilog)
	net "count[18]" in work.st_mult1(verilog)
	net "count[19]" in work.st_mult1(verilog)
	net "count[20]" in work.st_mult1(verilog)
	net "count[21]" in work.st_mult1(verilog)
	net "count[22]" in work.st_mult1(verilog)
	net "count[23]" in work.st_mult1(verilog)
	net "count[24]" in work.st_mult1(verilog)
	net "count[25]" in work.st_mult1(verilog)
	net "count[26]" in work.st_mult1(verilog)
	net "count[27]" in work.st_mult1(verilog)
	net "count[28]" in work.st_mult1(verilog)
	net "count[29]" in work.st_mult1(verilog)
	net "count[30]" in work.st_mult1(verilog)
	net "count[31]" in work.st_mult1(verilog)
	net "VCC" in work.st_mult1(verilog)
@W: BN137 :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":26:1:26:4|Found combinational loop during mapping at net state_temp[0]
33) instance work.st_mult1(verilog)-state_temp[0], output net "state_temp[0]" in work.st_mult1(verilog)
    input nets to instance:
	net "state_temp_1[0]" in work.st_mult1(verilog)
	net "un1_current_state[0]" in work.st_mult1(verilog)
	net "un1_current_state_5" in work.st_mult1(verilog)
@W: BN137 :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":26:1:26:4|Found combinational loop during mapping at net state_temp[1]
34) instance work.st_mult1(verilog)-state_temp[1], output net "state_temp[1]" in work.st_mult1(verilog)
    input nets to instance:
	net "state_temp_1[1]" in work.st_mult1(verilog)
	net "un1_current_state[0]" in work.st_mult1(verilog)
	net "un1_count18_1" in work.st_mult1(verilog)
	net "un1_current_state_3" in work.st_mult1(verilog)
End of loops
RTL optimization done.
Warning: Found 34 combinational loops!
         Each loop is reported with an instance in the loop
         and nets connected to that instance.
@W: BN137 :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":26:1:26:4|Found combinational loop during mapping at net count[0]
1) instance work.st_mult1(verilog)-count[31:0], output net "count[0]" in work.st_mult1(verilog)
    input nets to instance:
	net "un9_count[0]" in work.st_mult1(verilog)
	net "N_2" in work.st_mult1(verilog)
	net "N_3" in work.st_mult1(verilog)
	net "N_4" in work.st_mult1(verilog)
	net "un9_count[4]" in work.st_mult1(verilog)
	net "N_6" in work.st_mult1(verilog)
	net "N_7" in work.st_mult1(verilog)
	net "N_8" in work.st_mult1(verilog)
	net "N_9" in work.st_mult1(verilog)
	net "N_10" in work.st_mult1(verilog)
	net "N_11" in work.st_mult1(verilog)
	net "N_12" in work.st_mult1(verilog)
	net "N_13" in work.st_mult1(verilog)
	net "N_14" in work.st_mult1(verilog)
	net "N_15" in work.st_mult1(verilog)
	net "N_16" in work.st_mult1(verilog)
	net "N_17" in work.st_mult1(verilog)
	net "N_18" in work.st_mult1(verilog)
	net "N_19" in work.st_mult1(verilog)
	net "N_20" in work.st_mult1(verilog)
	net "N_21" in work.st_mult1(verilog)
	net "N_22" in work.st_mult1(verilog)
	net "N_23" in work.st_mult1(verilog)
	net "N_24" in work.st_mult1(verilog)
	net "N_25" in work.st_mult1(verilog)
	net "N_26" in work.st_mult1(verilog)
	net "N_27" in work.st_mult1(verilog)
	net "N_28" in work.st_mult1(verilog)
	net "N_29" in work.st_mult1(verilog)
	net "N_30" in work.st_mult1(verilog)
	net "N_31" in work.st_mult1(verilog)
	net "N_32" in work.st_mult1(verilog)
	net "un1_current_state_2" in work.st_mult1(verilog)
	net "state_temp_0_sqmuxa" in work.st_mult1(verilog)
@W: BN137 :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":52:12:52:19|Found combinational loop during mapping at net N_2
2) instance work.st_mult1(verilog)-un9_count[31:0], output net "N_2" in work.st_mult1(verilog)
    input nets to instance:
	net "N_35" in work.st_mult1(verilog)
	net "count[1]" in work.st_mult1(verilog)
	net "count[2]" in work.st_mult1(verilog)
	net "count[3]" in work.st_mult1(verilog)
	net "count[4]" in work.st_mult1(verilog)
	net "count[5]" in work.st_mult1(verilog)
	net "count[6]" in work.st_mult1(verilog)
	net "count[7]" in work.st_mult1(verilog)
	net "count[8]" in work.st_mult1(verilog)
	net "count[9]" in work.st_mult1(verilog)
	net "count[10]" in work.st_mult1(verilog)
	net "count[11]" in work.st_mult1(verilog)
	net "count[12]" in work.st_mult1(verilog)
	net "count[13]" in work.st_mult1(verilog)
	net "count[14]" in work.st_mult1(verilog)
	net "count[15]" in work.st_mult1(verilog)
	net "count[16]" in work.st_mult1(verilog)
	net "count[17]" in work.st_mult1(verilog)
	net "count[18]" in work.st_mult1(verilog)
	net "count[19]" in work.st_mult1(verilog)
	net "count[20]" in work.st_mult1(verilog)
	net "count[21]" in work.st_mult1(verilog)
	net "count[22]" in work.st_mult1(verilog)
	net "count[23]" in work.st_mult1(verilog)
	net "count[24]" in work.st_mult1(verilog)
	net "count[25]" in work.st_mult1(verilog)
	net "count[26]" in work.st_mult1(verilog)
	net "count[27]" in work.st_mult1(verilog)
	net "count[28]" in work.st_mult1(verilog)
	net "count[29]" in work.st_mult1(verilog)
	net "count[30]" in work.st_mult1(verilog)
	net "count[31]" in work.st_mult1(verilog)
	net "VCC" in work.st_mult1(verilog)
@W: BN137 :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":52:12:52:19|Found combinational loop during mapping at net N_3
3) instance work.st_mult1(verilog)-un9_count[31:0], output net "N_3" in work.st_mult1(verilog)
    input nets to instance:
	net "N_35" in work.st_mult1(verilog)
	net "count[1]" in work.st_mult1(verilog)
	net "count[2]" in work.st_mult1(verilog)
	net "count[3]" in work.st_mult1(verilog)
	net "count[4]" in work.st_mult1(verilog)
	net "count[5]" in work.st_mult1(verilog)
	net "count[6]" in work.st_mult1(verilog)
	net "count[7]" in work.st_mult1(verilog)
	net "count[8]" in work.st_mult1(verilog)
	net "count[9]" in work.st_mult1(verilog)
	net "count[10]" in work.st_mult1(verilog)
	net "count[11]" in work.st_mult1(verilog)
	net "count[12]" in work.st_mult1(verilog)
	net "count[13]" in work.st_mult1(verilog)
	net "count[14]" in work.st_mult1(verilog)
	net "count[15]" in work.st_mult1(verilog)
	net "count[16]" in work.st_mult1(verilog)
	net "count[17]" in work.st_mult1(verilog)
	net "count[18]" in work.st_mult1(verilog)
	net "count[19]" in work.st_mult1(verilog)
	net "count[20]" in work.st_mult1(verilog)
	net "count[21]" in work.st_mult1(verilog)
	net "count[22]" in work.st_mult1(verilog)
	net "count[23]" in work.st_mult1(verilog)
	net "count[24]" in work.st_mult1(verilog)
	net "count[25]" in work.st_mult1(verilog)
	net "count[26]" in work.st_mult1(verilog)
	net "count[27]" in work.st_mult1(verilog)
	net "count[28]" in work.st_mult1(verilog)
	net "count[29]" in work.st_mult1(verilog)
	net "count[30]" in work.st_mult1(verilog)
	net "count[31]" in work.st_mult1(verilog)
	net "VCC" in work.st_mult1(verilog)
@W: BN137 :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":52:12:52:19|Found combinational loop during mapping at net N_4
4) instance work.st_mult1(verilog)-un9_count[31:0], output net "N_4" in work.st_mult1(verilog)
    input nets to instance:
	net "N_35" in work.st_mult1(verilog)
	net "count[1]" in work.st_mult1(verilog)
	net "count[2]" in work.st_mult1(verilog)
	net "count[3]" in work.st_mult1(verilog)
	net "count[4]" in work.st_mult1(verilog)
	net "count[5]" in work.st_mult1(verilog)
	net "count[6]" in work.st_mult1(verilog)
	net "count[7]" in work.st_mult1(verilog)
	net "count[8]" in work.st_mult1(verilog)
	net "count[9]" in work.st_mult1(verilog)
	net "count[10]" in work.st_mult1(verilog)
	net "count[11]" in work.st_mult1(verilog)
	net "count[12]" in work.st_mult1(verilog)
	net "count[13]" in work.st_mult1(verilog)
	net "count[14]" in work.st_mult1(verilog)
	net "count[15]" in work.st_mult1(verilog)
	net "count[16]" in work.st_mult1(verilog)
	net "count[17]" in work.st_mult1(verilog)
	net "count[18]" in work.st_mult1(verilog)
	net "count[19]" in work.st_mult1(verilog)
	net "count[20]" in work.st_mult1(verilog)
	net "count[21]" in work.st_mult1(verilog)
	net "count[22]" in work.st_mult1(verilog)
	net "count[23]" in work.st_mult1(verilog)
	net "count[24]" in work.st_mult1(verilog)
	net "count[25]" in work.st_mult1(verilog)
	net "count[26]" in work.st_mult1(verilog)
	net "count[27]" in work.st_mult1(verilog)
	net "count[28]" in work.st_mult1(verilog)
	net "count[29]" in work.st_mult1(verilog)
	net "count[30]" in work.st_mult1(verilog)
	net "count[31]" in work.st_mult1(verilog)
	net "VCC" in work.st_mult1(verilog)
@W: BN137 :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":26:1:26:4|Found combinational loop during mapping at net count[4]
5) instance work.st_mult1(verilog)-count[31:0], output net "count[4]" in work.st_mult1(verilog)
    input nets to instance:
	net "un9_count[0]" in work.st_mult1(verilog)
	net "N_36" in work.st_mult1(verilog)
	net "N_37" in work.st_mult1(verilog)
	net "N_38" in work.st_mult1(verilog)
	net "un9_count[4]" in work.st_mult1(verilog)
	net "N_6" in work.st_mult1(verilog)
	net "N_7" in work.st_mult1(verilog)
	net "N_8" in work.st_mult1(verilog)
	net "N_9" in work.st_mult1(verilog)
	net "N_10" in work.st_mult1(verilog)
	net "N_11" in work.st_mult1(verilog)
	net "N_12" in work.st_mult1(verilog)
	net "N_13" in work.st_mult1(verilog)
	net "N_14" in work.st_mult1(verilog)
	net "N_15" in work.st_mult1(verilog)
	net "N_16" in work.st_mult1(verilog)
	net "N_17" in work.st_mult1(verilog)
	net "N_18" in work.st_mult1(verilog)
	net "N_19" in work.st_mult1(verilog)
	net "N_20" in work.st_mult1(verilog)
	net "N_21"